PNX1502E Datasheet, PDF (758/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 25: I²C Interface
3.1 Register Tables
Table 2: IIC Registers
Bit Symbol
Offset 0x04 5000
31:8 Unused
7
AA
Acces
s
Value
I2C CONTROL
-
R/W 0
6
EN
R/W 0
5
STA
R/W 0
4
STO
R
0
3
Unused
2:0 CR
-
R/W 100
Description
Ignore upon read. Write as zeroes.
IIC acknowledge bit
0 = Acknowledge not returned during acknowledge clock pulse
1 = Acknowledge returned during acknowledge clock pulse
IIC enable bit
0 = Disable IIC module
1 = Enable IIC module
IIC start bit
0 = Slave mode, accept transactions
1 = Master mode, generate start condition if bus is free
IIC stop bit
0 = Slave mode, accept transactions
1 = Generate stop condition on I²C bus when IIC module is
master.
Ignore upon read. Write as zeroes.
These three bits determine the serial clock frequency when
IIC module is in master mode. This field shall be changed
only when EN bit is 0. The IIC Clock is divided as follows to
achieve the desired frequency. The table assumes the IIC module
receives a 24 MHz clock from the Clock module.
0: 60 -> 400 KHz
1: 80 -> 300 KHz
2: 120 -> 200 KHz
3: 160 -> 150 KHz
4: 240 -> 100 KHz
5: 320 -> 75 KHz
6: 480 -> 50 KHz
7: 960 -> 25 KHz
Bit 7: AA Address Acknowledge
If the AA flag is set, an acknowledge (low level to SDA) will be returned during the
acknowledge clock pulse on the SCL line when:
• The “own slave address” has been received.
• The general call address has been received while the general call bit (GC) in the
ADR register is set.
• A data byte has been received while IIC module is in the master receiver mode.
• A data byte has been received while IIC module is in the addressed slave
receiver mode.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
25-8