PNX1502E Datasheet, PDF (387/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 11: QVCP
4.8.1 Layer Underflow
Any time the layer position has reached but the small 16-pixel FIFO at the end of
every layer pipe has run out of available pixels, underflow occurs.
4.8.2 Underflow Symptom
• Only portion of a picture is displayed or occasional blinking of picture happens
• Underflow interrupt bit is set.
4.8.3 Underflow Recovery
Should an underflow occur, the layer would fetch and dump remaining data for the
current field/frame. The next field/frame would be fetched and displayed as normal.
4.8.4 Underflow Trouble-shooting
• Check if the DMA source width settings (0x10,Ex08) matches the initial layer
width (0x10,Ex34)
• Check if the initial layer width (0x10,Ex34) matches the final layer width
(0x10,ExB4) for the non-scaled layer.
• Check if the final layer width (0x10,ExB4) is within acceptable cropping range for
LINT or HSRU scaling.
• Check whether the DMA start fetch (0x10,ExC8) is at line number too close to the
display position. Note that about 64 pixels is QVCP’s input-to-output latency. So,
depending on the system-memory latency, the DMA fetch should start as early as
possible, in order to make up for the request-to-data latency.
• Check if the system memory arbiter is giving high priority to QVCP.
• Check if QVCP demands exceed allocated memory bandwidth.
4.8.5 Underflow Handling
The underflow interrupt status would stay asserted until an interrupt-status-clear is
programmed.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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