PNX1502E Datasheet, PDF (118/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 3: System On Chip Resources
6.3.1 TM3260 System Parameters MMIO Registers
Table 7: TM3260 System Parameters MMIO Registers
Bit Symbol
Acces
s
Value
Description
System Module Registers
Offset 0x06 3700
TM32_CONTROL
31:4 Unused
-
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
3
TM32_APERT_MODIFI R/W 0x1
ABLE
TM3260 Aperture Modifiable.
This bit is usually written once at boot time.
The value of this bit can only be altered once.
• 0: Disables writes by the TM3260 to the MMIO registers
TM32_DRAM_HI, TM32_DRAM_LO, TM32_APERT_HI and
TM32_APERT_LO.
• 1: Enables writes by the TM3260 to the MMIO registers
TM32_DRAM_HI, TM32_DRAM_LO, TM32_APERT_HI and
TM32_APERT_LO.
2
TM32_LS_DBLLINE
R/W 0x1
TM3260 Load/Store Unit (i.e. Data Cache) Double Line Fill enable
• 0: Do not enable Double Line fills for the Load/Store Unit
• 1: Enable Double Line fills for the Load/Store Unit
1
TM32_IFU_DBLLINE R/W 0x1
TM3260 Instruction Fetch Unit (i.e. Instruction Cache) Double Line
Fill enable
• 0: Do not enable Double Line fills for the Instruction Fetch Unit
• 1: Enable Double Line fills for the Instruction Fetch Unit
0
TM32_PWRDWN_REQ R/W 0x0
TM3260 full powerdown request
Upon writes:
• 1->0: Request a TM3260 Power Up
• 0->1: Request a TM3260 Power Down
Upon reads
• Undefined
Offset 0x06 3704
TM32_STATUS
31:1 Unused
-
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
0
TM32_PWRDWN_ACK R
0x0
0: TM3260 is in full power mode.
1: TM3260 is in full powerdown mode.
7. Video Input and Output Routers
PNX15xx Series provides two groups of high speed pins to stream data or video in
and out. The input group of pins is prefixed by VDI, Video Data Input. The output
group is prefixed by VDO, Video Data Output. Each group is shared between two
modules. On the input side, VIP and FGPI get their pin allocation through the input
router. On the output side QVCP and FGPO get their pin assignment through the
output router. The input router is controlled by VDI_MODE. The output router is
controlled by the VDO_MODE.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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