PNX1502E Datasheet, PDF (226/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 7: PCI-XIO Module
DATA_DIR- AD8
Dir1/2
A1[0] _B1[0]
VCC
PCI AD[31:24]
VCC
10K
PCI AD[23:16]
XIO_SEL[1] - IDE_ENABLE
DD[7:0]
A1[7] B1[7]
74LS16245
A2[0] B2[0]
INTREQ
GPIO
DD[15:8]
A2[7] B2[7]
OE_n1/2
VCC VCC VCC VCC VCC
1K 1K 1K 1K 1K
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD0
OE1/2
74LS244
CS1
CS0
DA2
DA1
DA0
DIOW-
DIOR-
IORDY
SYS_RSTN_OUT
Buffer
RESET_n
Note the 10 K pullup required for INTREQ,
XIO_SEL and the 1.0 K pullup required for
DIOW-, DIOR- and IORDY.
Figure 11: Isolation Translation Logic
Data Transfer Operation
In PIO mode, data transfer to/from disk is done using read/write operations of the
command and control block registers. PI/PO protocol is explained in the ATA-2
specification.
All command block registers can be programmed using direct or indirect access in the
XIO block. All disk registers are programmed. When the disk is ready to transfer data,
DMA is enabled.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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