PNX1502E Datasheet, PDF (514/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 15: Audio Output
3.2 Reset-Related Issues
Audio Out is reset by the system reset signal or by writing AO_CTL.RESET = 1.
Either reset method sets all MMIO fields to their default values as indicated in the
Section 4. Register Descriptions.
When software reset is activated (AO_CTL.RESET = 1) the clock generation using
the values programmed in the internal MMIO register (SER_MASTER, AO_SERIAL,
...) is stopped since these values get reset. This causes the AO module to do not
have a clock anymore which does not complete the reset. Therefore before resetting
the AO module, the AO module should be clocked by the crystal 27 MHz clock.
Software must follow a series of steps to ensure that Software Reset happens
correctly:
1. Check to see if there is a valid clock present on the Audio Out external clock input.
2. If there is no clock, then write to the clocks block to switch the Audio Out block
clock input to the 27 MHz oscillator.
3. Apply Software Reset and poll the Reset bit until it is cleared.
4. Program the Clocks block to switch back to the external clock mode for the Audio
Out block.
Clocks are required to be running during HW/SW reset because synchronous reset is
used to initialize the logic. The unique feature with Audio is that unlike all other blocks
in the system, the Audio blocks default to the external clock source on any reset. If the
external clock does not exist when a HW reset is applied, then the logic is left
uninitialized without any indication.
3.3 Register Programming Guidelines
• When configuring the Audio Out, data framing options and DMA buffer
parameters must be programmed before enabling transmission.
3.4 Power Management
Audio Out has no internal powerdown functionality, however the chip power
management software can remove the main block level clock to Audio Out. If the
Audio Out module enters a powerdown state, SCK, WS and SD[x] hold their value
stable but OSCLK continues to provide a D/A converter oversampling clock.
Once the system wakes up, the signals resume their original transitions at the point
where they were halted. The external D/A converter subsystem will most likely be
confused by this behavior, so it is recommended that Audio Out transmissions be
stopped (by deactivating TRANS_ENABLE) prior to software enable of Audio Out
powerdown.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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