PNX1502E Datasheet, PDF (459/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 13: FGPO: Fast General Purpose Output
2. Functional Description
Table 1: Module signal pins
Signal
Type Description
clk_fgpo
input From Clock Module. External FGPO clock on VDO_C2 pin is connected to the Clock Module.
fgpo_rec_sync
input
FGPO data and control signals are output at each rising edge on clk_fgpo. Use the PNX15xx
Series Clock Module to change clk_fgpo characteristics.
From External PAD.
fgpo_buf_sync
input
In external record/message sync mode a programmable transition on this pin will trigger the
output of a record or message after a synchronization delay of 4 FGPO clock cycles. If the
transition occurs before the FGPO has finished the output of a previous record or message,
the transition will be ignored.
From External PAD.
fgpo_start
or
fgpo_rec_start
output
In external buffer sync mode a programmable transition on this pin will start a new buffer after
a synchronization delay of 4 FGPO clock cycles. If the transition occurs before the FGPO has
finished the current buffer, the transition will be ignored.
To External PAD VDO_D[32] via Output Router.
Message Passing Mode:
A positive pulse output on this pin indicates the start of a message. The pulse may be
programmed to occur one clock before or at the same clock with the first valid data sample.
Record Mode:
A positive pulse output on this pin indicates the start of a record. The pulse may be
programmed to occur one clock before or at the same clock with the first valid data sample
or
A positive pulse lasting as long as valid data samples are output.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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