PNX1502E Datasheet, PDF (713/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 23: LAN100 — Ethernet Media Access Controller
been reached and the status of the third fragment is written. The third fragment’s
status word will have the Last bit set to 1 and the EntryLevel equal to 2 (for a value of
3, because of –1 encoding).
The next packet received from the MII interface will be written to the fourth fragment
buffer, therefore five bytes of the third buffer will be unused.
The Rx DMA manager checks to make sure receive data and status data have been
committed to memory. Only if memory acknowledges that the data has been
committed to memory will the RxProduceIndex be updated and the interrupt flags be
forwarded to the IntStatus register. The LAN100 tags receive data and statuses
continuously but does not necessarily tag every data and every status individually.
After committing status of the fragments to memory the LAN100 will trigger a
RxDoneInt interrupt, which triggers the device driver to inspect the status information.
In this example all descriptors have the Interrupt bit set in the Control word, so all
descriptors will generate an interrupt after committing data and status to memory.
In this example, the receive function of the LAN100 cannot read new descriptors as
long as the device driver does not increment the RxConsumeIndex because the
descriptor array is full (even though one descriptor is not programmed yet, see
Section 5.2.4 on page 23-35). Only after the device driver has forwarded the receive
data to application software and after the device driver has updated the
RxConsumeIndex by incrementing it by the number of received fragments (3 in this
case) can the LAN100 continue reading descriptors and receive data.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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