PNX1502E Datasheet, PDF (135/819 Pages) NXP Semiconductors – Connected Media Processor

Chapter 4: Reset
PNX15xx Series Data Book – Volume 1 of 1
Rev. 2 — 1 December 2004
Product data sheet
1. Introduction
The Reset module initiates life for the PNX15xx Series system since it generates all
reset signals required for a correct initialization of the entire system (may include
board devices).
• It sends reset signals to all DCS bus modules and the TM3260 CPU.
• It sends a reset signal on the SYS_RST_OUT_N pin that can be used by external
board devices. This signal is then de-asserted by software.
These resets signals are triggered by hardware (one type) or by software (three
types):
• Hardware external reset input to the PNX15xx Series through the pins,
POR_IN_N or RESET_IN_N.
• Software assert and release of the SYS_RST_OUT_N reset pin through a write
to an MMIO register write.
• Software programmable watchdog timer which asserts the same reset signals as
the hardware reset induced by the assertion of RESET_IN_N pin when a time-out
is reached.
• Software PNX15xx Series system reset which asserts the same reset signals as
the hardware reset induced by the assertion of RESET_IN_N pin.
RST_CAUSE MMIO register holds the cause of the previous reset which allows the
software to know what happened before.
2. Functional Description
The Reset module generates three different reset signals to fully initialize a PNX15xx
Series system:
• jtag_rst_n. This signal is used internally to reset the JTAG state machine. The
signal is only asserted if the POR_IN_N pin is asserted. Therefore the only mean
to reset the JTAG state machine of PNX15xx Series is by asserting the
POR_IN_N pin.Figure 1
Remark: The JTAG state machine can also be reset through the JTAG pins.