PNX1502E Datasheet, PDF (479/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 14: FGPI: Fast General Purpose Interface
Refer to Figure 2. This block diagram shows the basic sections of the FGPI module.
DTL
MMIO
I/F
8/16/32
fgpi_data
DATA
PACKER
fgpi_d_valid
32
fgpi_start
fgpi_stop
DMA
ENGINE
32
DTL
INITIATOR
BUFFER
SYNC
32
TIMESTAMP
LENGTH
DTL
INITIATOR
Figure 2: FGPI Module Block Diagram
1.2 VDI to FGPI pin mapping
VDI_D[32] maps to fgpi_start (fgpi_rec_start)
VDI_D[33] maps to fgpi_stop (fgpi_buf_start)
VDI_V2 maps to fgpi_d_valid
VDI_C2 maps to clock module fgpi_clk input
VDI_D[31:0] mapping depends on the VDI_MODE (Input Router) register settings as
described in the Chapter 3 System On Chip Resources.
1.3 DTL MMIO Interface
This block contains all of the programmable registers used by the FGPI module
accessed through the MMIO bus. Refer to Section 4. on page 14-18 for register
descriptions. This block also handles clock domain crossing between the MMIO bus
clock and the FGPI module clock.
1.4 Data Packer
This block is used to pack incoming data samples into 32-bit words to be sent to main
memory. This module also informs the DMA Engine when a valid 32-bit data word is
ready to be loaded into the MTL DTL adapters FIFO via the DTL Initiators.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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