PNX1502E Datasheet, PDF (332/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 9: DDR Controller
Table 9: Register Description
Bit Symbol
Access Value Description
2
DDR_HALVE_WIDTH R/W 0
‘0’: The complete “dq” bus of the DDR interface is used.
‘1’: Only the lower halve of the data bus of the DDR interface is
used. Only DDR data bits “MM_DATA[15:0]” are in use.
1
SPEC_AUTO_PR
R/W 0
‘0’: Speculative auto precharge is off.
‘1’: Speculative auto precharge is on.
0
START
R/W 0
‘1’: Start DDR controller. When started, controller will return the
start bit to ‘0’.
Offset 0x06 5004
DDR_DEF_BANK_SWITCH
Note: Addressing modes 2048_MODE, 1024_MODE, and the interleaving mode defined by the BANK_SWITCH field are
mutually exclusive. Setting 2048_MODE to ‘1’ sets the IP_2031 into 2048 byte stride mode, and makes the values of
1024_MODE and BANK_SWITCH “don’t cares” for the IP_2031. When 2048_MODE is ‘0’ and 1024_MODE is ‘1’, the
IP_2031 is set into 1024 byte stride mode, which makes the value of BANK_SWITCH a “don’t care” for the IP_2031.
31:4 Unused
R
-
These bits should be ignored when read and written as 0s.
3:0 BANK_SWITCH
R/W 3
Switch banks every 2^BANK_SWITCH columns (each column has
a width of 4 bytes). For 32-byte interleaving set this value equal to
0x3. For full page/row interleaving set this value equal to the column
width value. Only the following values are supported:
0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, and 0xb.
Recommended value is 3.
Offset 0x06 5008
AUTO_HALT_LIMIT
31 PON
R/W 0
Controls PON signal of the SSTL_2 PADs:
‘1’: May be set to ‘1’ when the DDR devices are sent into self-
refresh mode, i.e. after a HALT command.
‘0’: Normal operation: must be set back to ‘0’ before enabling again
the DDR devices, i.e. before the UNHALT command.
30:0 LIMIT
R/W -
After LIMIT amount of IP_2031 idle cycles, automatic halt kicks in.
The address locations of the DDR memory ranks are determined by registers RANK0_ADDR_LO, RANK0_ADDR_HI, and
RANK1_ADDR_HI. Addresses in [RANK0_ADDR_LO, RANK0_ADDR_HI] are directed to rank 0, addresses in
[RANK0_ADDR_HI, RANK1_ADDR_HI] are directed to rank 1. Addresses outside the two ranks are said to cause an
address error.
Offset 0x06 5010
RANK0_ADDR_LO
31:0 ADDR_LO
R/W 0x0000 Address at which the DDR rank 0 address space starts.
0000
Offset 0x06 5014
RANK0_ADDR_HI
31:0 ADDR_HI
R/W 0xFFFF Address at which the DDR rank 0 address space ends.
FFFF
Offset 0x06 5018
RANK1_ADDR_HI
31:0 ADDR_HI
R/W 0xFFFF Address at which the DDR rank 1 address space ends.
FFFF
Dimension of DDR Memories
Offset 0x06 5080
DDR_MR
31:13 Unused
R
-
These bits should be ignored when read, and written as 0’s.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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