PNX1502E Datasheet, PDF (43/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 1: Integrated Circuit Data
Table 4: PNX1500 Interface
Pin Name
BGA Pad
Ball Type
I/O GPIO
Type #
P Description
GPIO06/CLOCK06
GPIO05/CLOCK05
GPIO04/CLOCK04
B9
BPTS1CHP I/O/D 6 U Used as GPIO pins. These pins can also be used to
A8 BPX2T14MCP I/O/D 5 U ^{output internally generated clocks for the external}
A7
BPTS1CHP
I/O/D
4
U
components present on the board. These GPIO
pins can also be used as clocks for sampling or
pattern generation in the GPIO module
(Section 2.11.2 on page 5-20). GPIO05/
GCLOCK05 requires a board level 27-33 Ω series
resistor to reduce ringing.
GPIO03/CLOCK03/
BOOT_MODE03
A4
BPTS1CHP I/O/D 3 D After the power up and boot sequence, this pin
functions as a GPIO[3] pin. This pin can also be
used as a clock for sampling or pattern generation
in the GPIO module. This GPIO pin may be
strapped with a resistor to VDD or VSS to
determine the PNX1500 boot mode upon reset.
GPIO02/CLOCK02/
BOOT_MODE02
GPIO01/CLOCK01/
BOOT_MODE01
GPIO00/CLOCK00/
BOOT_MODE00
A3
BPTS1CHP I/O/D 2 U After the power up and boot sequence, these pins
-
-
-
- - are configured as GPIO[2:0] pins. These pins can
B3
BPTS1CHP I/O/D 1 U ^{also be used as clocks for sampling or pattern}
-
-
-
- - ^{generation in the GPIO module. These GPIO pins}
B4
BPTS1CHP I/O/D
0
U
may be strapped with resistors to VDD or VSS to
determine the PNX1500 boot mode upon reset.
-
-
-
--
JTAG Interface (debug access port and 1149.1 boundary scan port)
JTAG_TDI
A1
IPCHP
IN - U JTAG Test Data Input.
JTAG_TDO
D6
BPTS3CHP
O
- - JTAG Test Data Output. This pin can either be an
output, or float. It is never an input.
JTAG_TCK
B1
IPCP
IN - U JTAG Test Clock Input.
JTAG_TMS
D5
IPCHP
IN - U JTAG Test Mode Select Input.
Power Supplies and Ground
Refer to Section 10. on page 1-43
for board level connection and decoupling associated with these pins.
VDDA
A10
APOD
PWR - - Analog, quiescent VDD, 1.2-1.3 V. Refer to
Figure 25 for board level connections.
VSSA_1.2
C11
APOD
GND - - Analog, quiescent ground for the 1.2 V analog
supply. Refer to Figure 25 for board level
connections.
VCCA[]
-
APOD
PWR - - Analog, quiescent VCCP, 3.3 V. Refer to Figure 24
for board level connections.
VSSA[]
-
APOD
GND - - Analog, quiescent ground. Refer to Figure 24 for
board level connections.
VCCP[]
-
VDDE3V3 PWR - - 3.3 V I/O power supply for peripherals I/Os.
VCCM[]
-
VDDE3V3 PWR - - 2.5 V power supply for the memory I/Os (3.3 V
capable of ATE, not for functional operation).
VDD[]
-
VDDI
PWR - - 1.2-1.3 V core power supply.
VSS[]
-
VSSIS
GND - - Ground for the core.
VSS[]
-
VSSE
GND - - Ground for the memory I/Os.
VSS[]
-
VSSE
GND - - Ground for the peripherals I/Os.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
1-17