PNX1502E Datasheet, PDF (638/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 20: 2D Drawing Engine
Table 31: PanicControl
Bit Symbol
Offset 0x04 F804
31:8 Reserved
7:0 RST
Acces
s
PanicControl
W
Value
-
Description
Used to reset the state machines in the Drawing Engine. Writing
0x0000_0001 to this register will halt the Drawing Engine and place
it in an idle state. Writing 0x0000_0000 will allow the DE to be
reprogrammed and resume normal operation. It may be necessary
for software to implement a delay between setting the RST signal to
1 and resetting it to 0.
This register is currently used to reset the state machines in the drawing engine. It
does not reset any other registers in the Engine.
Table 32: EngineConfig
Bit Symbol
Acces
s
Value
Offset 0x04 F808
EngineConfig
31:11 Reserved
10 IRQ_CLR
R/W 0
9
BMODE
R/W 0
8
IRQ_EN
7:3 Reserved
R/W 0
Description
IRQ_CLR (bit 10) is a self-clearing bit used to reset Drawing Engine
IRQ flip-flop. The IRQ flip-flop is set when the DEBusy bit in the
EngineStatus register transitions from 1 to 0. It is cleared under
software control by setting IRQ_CLR to 1. See BMODE for a
description of DEBusy.
BMODE selects between two slightly different behaviors of DEBusy
and DEDone (EngineStatus register).
0=the DEBusy bit is set to 1 when the BLT/vector state machine
becomes active i.e., a drawing operation is starting. The bit is
cleared only when the state machine is idle, all memory writes are
completed, and the command FIFO is empty.
1=the DEBusy bit is set whenever the BLT/vector state machine is
active OR the command FIFO is not empty. The DEBusy bit will be
cleared when the engine is idle AND the command FIFO is empty.
Note that in this mode, the Draw Engine will go busy whenever a
register is loaded. Using interrupts can be tricky in this mode.
IRQ_EN (bit 8) is used to enable the interrupt signal leaving the
Drawing Engine module. When IRQ_EN is set to a 1, the interrupt
signal is enabled. When set to 0, the interrupt signal leaving the
Drawing Engine is masked. The IRQ_EN does not affect the actual
IRQ flip-flop. It merely masks the IRQ bit leaving the module.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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