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PNX1502E Datasheet, PDF (310/819 Pages) NXP Semiconductors – Connected Media Processor | |||
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Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 9: DDR Controller
There are two mechanisms available in the arbitration: windows and account budgets.
Windows provide the basic means to allocate DDR bandwidth. A window is deï¬ned in
terms of DDR controller clock cycles. Windows are deï¬ned for DMA trafï¬c
(HRT_WINDOW) and CPU trafï¬c (CPU_WINDOW), and they alternate with each
other in time. During an HRT_WINDOW, the DMA trafï¬c is given priority by the
arbitration scheme. During a CPU_WINDOW, the CPU trafï¬c is given priority by the
arbitration scheme.
As implied by the names CPU_WINDOW and HRT_WINDOW, windows have been
introduced to divide DDR bandwidth between CPU trafï¬c and Hard Real-Time (HRT)
DMA trafï¬c. Typically, in an SOC a third type of trafï¬c is present as well: Soft
Real_time (SRT) DMA trafï¬c. This type of trafï¬c usually has less hard real-time
constraints than HRT DMA trafï¬c i.e., the bandwidth requirements can be averaged
over a much larger time period (several windows) than with HRT. However, it is still
necessary to ensure that this type of trafï¬c receives DDR memory bandwidth. To this
end, a CPU account is introduced.
The CPU account limits (budgets) the memory bandwidth consumption by the CPU
trafï¬c to ensure that SRT DMA trafï¬c receives enough memory bandwidth. The CPU
account is deï¬ned by CPU_RATIO, CPU_LIMIT, CPU_CLIP and CPU_DECR.
The value CPU_RATIO controls how much bandwidth the CPU can get. The value
CPU_LIMIT controls how many DDR bursts the CPU can take back-to-back before
the CPU is out of budget. The value CPU_CLIP controls how much debt the CPU is
allowed to build up. CPU_DECR is made programmable so that the accuracy of the
accounting can be increased. This is especially needed when using dynamic ratios
(see Section ).
When the internal account exceeds CPU_LIMIT, DMA trafï¬c is given higher priority
than CPU trafï¬c, independent of which window is active. The internal account is a
saturated counter, that is, it will not wrap around on an underï¬ow or overï¬ow. For
every DDR controller memory clock cycle, the internal counter is decremented by
CPU_DECR. Whenever a CPU DDR burst is started, the internal counter is
incremented by an amount equal to the amount of data transfer cycles, plus the value
of CPU_RATIO, except when a CPU MTL transaction is âfor freeâ.
A CPU MTL transaction is for free if it starts while the account value is above the
CPU_CLIP value1. If a DDR burst is for free, then the account gets incremented by an
amount equal to the amount of data transfer cycles, without the CPU_RATIO. The
CPU_CLIP value should always be set equal or higher than CPU_LIMIT, otherwise
CPU_LIMIT would never be reached.
By means of the accounting mechanism, the CPU bandwidth can be budgeted. In the
CPU_WINDOW a CPU normally has priority over DMA. For every clock cycle the
CPU account gets funded with CPU_DECR. For every CPU DDR burst, the costs of
that burst, deï¬ned as CPU_RATIO plus data transfer cycles, are accounted for. When
the CPU account runs out of budget (account value above CPU_LIMIT), then DMA
will get priority over the CPU.
1. If pre-empting of the MTL transaction is not allowed, then all DDR bursts from one MTL transaction are treated the same. So if the
first DDR burst is (not) for free then the other DDR bursts for the same MTL transactions will also be (not) for free. If pre-emption of
the MTL transaction is allowed, then the âfor freeâ decision is made separately for each DDR burst.
12NC 9397 750 14321
Product data sheet
Rev. 2 â 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
9-4
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