PNX1502E Datasheet, PDF (611/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 20: 2D Drawing Engine
2.1 2D Drawing Engine Block Level Diagram
Internal MMIO Bus
Host Interface
Source
State
Registers
Dest
State
Bit Blit
Engine
Address Stepper
Vector
Engine
Foreground
Color
Expand
Rotator
Memif Interface
Pattern
FIFO
Source
FIFO
Dest
FIFO
Write Datapath
Memory
Read
Data
Transparency Byte Masking
Control
Address
Byte Enables
Write Data
Memory I/F GIZMO
Figure 1: 2D Drawing Engine Block Diagram
2.2 Architecture
2.2.1 Registers
This block contains the MMIO registers for the drawing engine.
2.2.2 Host Interface
This block synchronizes and FIFOs data from the internal MMIO bus. Host data and
patterns pass through this block as well as register operations.
2.2.3 Color Expand
Monochrome bitmaps, fonts, and patterns pass through this block and are expanded
to the appropriate full color depth. The color expanded data will then be sent to the
rotator block for alignment or loaded into the Pattern RAM. Full color data also passes
through this block and is combined from DWORDs into QWORDS. Alpha data from the
host is converted to the appropriate format by this block.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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