SAA7196 Datasheet, PDF (7/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
6 PINNING
SYMBOL
XTAL
XTALI
SDA
SCL
I²CSA
CHR0
CHR1
CHR2
CHR3
CHR4
CHR5
CHR6
CHR7
V_DDD1
CTST
V_SSD1
CVBS0
CVBS1
CVBS2
CVBS3
CVBS4
CVBS5
CVBS6
CVBS7
HSY
HCL
V_DDA
LFCO
V_SSA
V_SSD2
V_DDD2
GPSW2
GPSW1
RTS1
RTS0
RES
CGCE
CREF
PIN
STATUS
DESCRIPTION
1
O
26.8 MHz crystal oscillator output, not used if TTL clock signal is used
2
I
26.8 MHz crystal oscillator input or external clock input (TTL, square wave)
3
I/O
I²C-bus data line
4
I
I²C-bus clock line
5
I
I²C-bus set address
6
I
digital chrominance input signal (bit 0)
7
I
digital chrominance input signal (bit 1)
8
I
digital chrominance input signal (bit 2)
9
I
digital chrominance input signal (bit 3)
10
I
digital chrominance input signal (bit 4)
11
I
digital chrominance input signal (bit 5)
12
I
digital chrominance input signal (bit 6)
13
I
digital chrominance input signal (bit 7)
14
−
+5 V digital supply voltage 1
15
−
connected to ground (clock test pin)
16
−
digital ground 1 (0 V)
17
I
digital CVBS input signal (bit 0)
18
I
digital CVBS input signal (bit 1)
19
I
digital CVBS input signal (bit 2)
20
I
digital CVBS input signal (bit 3)
21
I
digital CVBS input signal (bit 4)
22
I
digital CVBS input signal (bit 5)
23
I
digital CVBS input signal (bit 6)
24
I
digital CVBS input signal (bit 7)
25
O
horizontal sync indicator output (programmable)
26
O
horizontal clamping pulse output (programmable)
27
−
+5 V analog supply voltage
28
O
line frequency control output signal to CGC
(multiple of present line frequency)
29
−
analog ground (0 V)
30
−
digital ground 2 (0 V)
31
−
+5 V digital supply voltage 2
32
O
general purpose output 2 (controllable via I²C-bus)
33
O
general purpose output 1 (controllable via I²C-bus)
34
O
real time status output 1; controlled by bit RTSE
35
O
real time status output 0; controlled by bit RTSE
36
O
reset output, active LOW
37
I
enable input for internal CGC (connected to +5 V)
38
O
clock qualifier output (test only)
1996 Nov 04
7