SAA7196 Datasheet, PDF (21/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
handbo_do_ik_g,_itf_aul_ll pagewidth
signal
value +254
+235
white 100%
digital
signal
value +254
+240
+212
blue 100%
digital
signal
value +254
+240
blue 75%
+212
red 100%
red 75%
+128
luminance
levels
+16
black
1
a. Y signal range.
+128
U-component
levels
+128
V-component
levels
+44
yellow 75%
+44
cyan 75%
+16
yellow 100%
+16
cyan 100%
1
1
MHA390
b. U signal range (B − Y).
c. V signal range (R − Y).
Fig.10 Input and output signal levels on expansion port.
7.3.3 RTCO OUTPUT PIN 44
This real-time control and status output signal contains
serial information about actual system clock, subcarrier
frequency and PAL/SECAM sequence (see Fig.11).
The signal can be used for various applications in external
circuits, e.g. in a digital encoder to achieve ‘clean’
encoding.
7.3.4 RTS1 AND RTS0 OUTPUTS (PINS 34 AND 35)
These outputs can be configured in two modes dependent
on bit RTSE (subaddress 0D):
• RTSE = 0: the output RTS0 contains the odd/even field
identification bit (HIGH equals odd); output RTS1
contains the inverted PAL/SECAM sequence bit [HIGH
equals non-inverted (R − Y)-line/DB-line]
• RTSE = 1: the output RTS0 contains the horizontal lock
bit (HIGH equals PLL locked); output RTS1 contains the
vertical detection bit (HIGH equals vertical sync
detected).
1996 Nov 04
21