SAA7196 Datasheet, PDF (44/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
Table 21 Automatic gain control (AGC filter)
BIT
LFIS1
0
0
1
1
LFIS0
0
1
0
1
LOOP FILTER TIME CONSTANT
slow
medium
fast
actual gain stored
(for test purposes only)
Table 22 General purpose switches
BIT
GPSW2 (PIN 32)
0
0
1
1
GPSW1 (PIN 33)
0
1
0
1
SET PORT OUTPUT PINS
use is dependent on application
Table 23 Luminance delay compensation
YDEL2
0
0
0
0
1
1
1
1
BIT
YDEL1
0
0
1
1
0
0
1
1
Note
1. Step size = 2/LCC = 67.8 ns for 50 Hz and 81.5 ns for 60 Hz.
YDEL0
0
1
0
1
0
1
0
1
DELAY⁽¹⁾
0 × 2/LCC
+1 × 2/LCC
+2 × 2/LCC
+3 × 2/LCC
−4 × 2/LCC
−3 × 2/LCC
−2 × 2/LCC
−1 × 2/LCC
1996 Nov 04
44