SAA7196 Datasheet, PDF (41/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
SUBADDRESS
CKTQ4 to CKTQ0
‘08’
CKTS4 to CKTS0
‘09’
PLSE7 to PLSE0
‘0A’
SESE7 to SESE0
‘0B’
COLO
‘0C’
LFIS1 to LFIS0
‘0C’
VTRC
‘0D’
RTSE
‘0D’
HRMV
‘0D’
SSTB
SECS
‘0D’
HPLL
‘0E’
OECL
‘0E’
OEHV
‘0E’
OEYC
‘0E’
DESCRIPTION
Colour-killer threshold QAM (PAL, NTSC) from approximately −30 dB to −18 dB equals data
bytes F8H to 07H.
Colour-killer threshold SECAM from approximately −30 dB to −18 dB equals data bytes
F8H to 07H.
PAL switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction)
equals FFH to 00H, MEDIUM equals 80.
SECAM switch sensitivity from LOW to HIGH (HIGH means immediate sequence correction)
equals FFH to 00H, MEDIUM equals 80.
colour-on bit
0 = automatic colour-killer
1 = forced colour-on
Automatic gain control (AGC filter); see Table 21.
VTR/TV mode bit
0 = TV mode
1 = VTR mode
real time output mode select bit
0 = PLIN switched to output RTS1 (pin 34); ODD switched to RTS0 (pin 35)
1 = HL switched to output RTS1 (pin 34); VL switched to RTS0 (pin 35)
HREF position select
0 = default
1 = HREF is 8 × LLC2 clocks earlier
status byte select
0 = status byte 0 is selected
1 = status byte 1 is selected
SECAM mode bit
0 = other standards
1 = SECAM
horizontal clock PLL
0 = PLL closed
1 = PLL open and horizontal frequency fixed
select internal/external clock source
0 = LLCB and CREFB are inputs
1 = LLCB and CREFB are outputs
output enable of horizontal/vertical sync
0 = HS, HREF and VS pins are inputs (outputs high-impedance)
1 = HS, HREF and VS pins are outputs
data output YUV15 to YUV0 enable
0 = data pins are inputs
1 = data pins are controlled by DIR (pin 95)
1996 Nov 04
41