SAA7196 Datasheet, PDF (26/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
It means:
HFL = 1 at the rising edge of INCADR: the ‘end of line’
is reached; request for line address increment
HFL = 0 at the rising edge of INCADR: the ‘end of
field/frame’ is reached; request for line and pixel
address reset.
7.4.10 TRANSPARENT DATA TRANSFER MODE
Data transfer on the VRAM port can be achieved
synchronously (TTR = 1) controlled by output reference
signals on outputs VRO7 to VRO0, and a continuous clock
rate of ¹â„₂LLC on input VCLK. The SAA7196 delivers a
continuously processed data stream. Therefore, the
extended formats of the VRAM output port are selected (bit
EFE = 1; see Table 10).
The output signals VRO7 to VRO0 have to be used to
buffer qualified preprocessed RGB or YUV video data.
To avoid read/write collision at the internal FIFO, the VCLK
timing and polarity must accord to the CREFB
specification.
The YUV data is only valid in qualified time slots. Control
output signals are (see Table 10 and Fig.16):
• α: keying signal of the chroma keyer
• O/E: odd/even field bit according to the internal field
processing
• VGT: vertical gate signal, ‘1’ marks the scaling window
in vertical direction from YO to (YO + YS) lines, cut by
VS
• HGT: horizontal gate signal, ‘1’ marks horizontal
direction from XO to (XO + XS) lines, cut by HREF
• HRF: delay compensated horizontal reference signal
• LNQ: line qualifier signal, active polarity is defined by bit
QPL
• PXQ: pixel qualifier signal, active polarity is defined by
bit QPP.
7.4.10.1 Interlaced processing
(OF bits, subaddress 20)
To support correct interlaced data storage, the scaler
delivers two INCADR/HFL sequences in each qualified
line and an additional INCADR/HFL sequence after the
vertical reset sequence at the beginning of an ODD field.
Thereby, the scaled lines are automatically stored in the
right sequence.
7.4.10.2 INCADR timing
The distance from the last half-full request (HFL) to the
INCADR pulse may be longer than 64 × LLC. The state of
HFL is defined for minimum 2 × LLC afterwards.
7.4.10.3 Monochrome format (see Table 10)
In case of TTR = 1 and EFE = 1 is Ya = Yb.
7.4.10.4 VRAM port specifications
Table 7 VMUX control; note 1
BIT VOF
0
0
1
X
Note
1. X = don’t care.
VOE (PIN 53)
0
0
0
1
VMUX (PIN 46)
0
1
X
X
VRAM BUS
VRO31 to VRO16
VRO15 to VRO0
3-state
active
active
3-state
active
3-state
active
3-state
1996 Nov 04
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