SAA7196 Datasheet, PDF (45/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
Table 24 Vertical noise reduction
BIT
VNOI1
0
0
1
1
VNOI0
0
1
0
1
MODE
normal
searching window
free-running mode
vertical noise reduction bypassed
Table 25 Chrominance gain control; note 1
BIT
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
.
.
.
.
.
.
.
.
0
1
0
1
1
0
0
1
.
.
.
.
.
.
.
.
0
0
1
0
1
1
0
0
.
.
.
.
.
.
.
.
0
0
0
0
0
0
0
0
Note
1. Default programmed values dependent on application.
GAIN
maximum gain
to
CCIR level for PAL
to
CCIR level for NTSC
to
minimum gain
1996 Nov 04
45