SAA7196 Datasheet, PDF (53/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
Table 30 Function of the register bits of Table 29 for subaddresses ‘20’ to ‘30’
SUBADDRESS
RTB
‘20’
OF1 to OF0
VPE
LW1 to LW0
‘20’
FS1 to FS0
XD9 to XD0
‘21 and 24’
XS9 to XS0
‘22 and 24’
XO8 to XO0
‘23 and 24’
HF2 to HF0
‘24’
YD9 to YD0
‘25 and 28’
YS9 to YS0
‘26 and 28’
YO8 to YO0
‘27 and 28’
AFS
‘28’
VP1 to VP0
VS8 to VS0
‘29 and 2B’
DESCRIPTION
ROM table bypass switch
0 = anti-gamma ROM active
1 = table is bypassed
set output field mode; see Table 31
VRAM port outputs enable
0 = HFL and INCADR inactive (HFL = LOW, INCADR = HIGH); VRO outputs in 3-state
1 = HFL and INCADR enabled; VRO outputs dependent on VOE
first pixel position in VRO data
FS1 = 0; FS0 = 0 (RGB) and FS1 = 0; FS0 = 1 (YUV); see Table 32
FS1 = 1; FS0 = 1 (monochrome); see Table 33
FIFO output register format select (bit EFE see ‘30’); see Table 34
pixel number per line (straight binary) on output (VRO): 00 0000 0000 to 11 1111 1111
(number of XS pixels as a maximum; take care of vertical processing)
pixel number per line (straight binary) on inputs (YIN and UVIN):
00 0000 0000 to 11 1111 1111 (number of input pixels per line as a maximum; take care of
vertical processing)
Horizontal start position (straight binary) of scaling window (take care of active pixel number
per line): start with the 1st pixel after HREF rise = 0 0000 0011 to 1 1111 1111 (003 to 1FF).
Window start and window end may be cut by internal delay compensated HREF = 0 phase.
Horizontal decimation filter; the filter coefficients are related to the luminance path. The filter
coefficient may differ from upper table when a combination with vertical Y processing and
adaptive modes are provided. See Table 35.
line number per output field (straight binary):
00 0000 0000 to 11 1111 1111 (number of YS lines as a maximum)
line number per input field (straight binary)
00 0000 0000 for 0 line
11 1111 1111 for 1023 lines (maximum = number of lines/field − 3)
Vertical start of scaling window [take care of active line number per field (straight binary);
window start and window end may be cut by the external VS signal]
0 0000 0000; start with 3rd line after the rising slope of VS
0 0000 0011; start with 1st line after the falling slope of nominal VS (7151B, 7191B input)
1 1111 1111; 511 + 3 lines after the rising slope of VS (maximum value)
adaptive filter switch
0 = off; use VP1, VP0 and HF2 to HF0 bits
1 = on; filter characteristics are selected by the scaler
vertical luminance data processing; see Table 36
vertical bypass start, sets begin of the bypass region (straight binary); scaling region overrides
bypass region (YO bits)
0 0000 0000; start with 3rd line after the rising slope of VS
0 0000 0011; start with 1st line after the falling slope of nominal VS (7151B, 7191B input)
1 1111 1111; 511 + 3 lines after the rising slope of VS (maximum value)
1996 Nov 04
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