SAA7196 Datasheet, PDF (25/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
7.4.6 OUTPUT DATA REPRESENTATION AND LEVELS
Output data representation of the YUV data can be
modified by bit MCT (subaddress 30). The DC gain is 1 for
YUV input data. The corresponding RGB levels are
defined by the matrix equations; they are limited to the
range of 1 to 254 in the 8-bit domain according to CCIR
601. In the event the YUV or monochrome luminance
output formats are selected and bit LLV = 1, the luminance
levels can be limited to:
• 16 (239) = black
• 235 (20) = white
• (...) = gray scale luminance levels.
For the 5-bit RGB formats a truncation from 8-bit to 5-bit
word width is implemented. Fill values are inserted
dependent on long word position and destination size
(see Section 7.4.9):
• ‘1’ for 24-bit RGB, Y and two’s complement UV
• ‘128’ for UV (straight binary)
• ‘254’ in 8-bit gray scale format.
7.4.7 OUTPUT FIFO REGISTER AND VRAM PORT
The output FIFO register is the buffer between the video
data stream and the VRAM data input port. Resized video
data are buffered and formatted. 32-, 24- and 16-bit video
data modes are supported. The various formats are
selected by the bits EFE, VOF, FS1 and FS0. VRAM port
formats are shown in Tables 7, 8 and 9. The FIFO register
capacity is 16 words × 32-bit (for 32-, 24- or 16-bit video
data).
The I²C bits LW1 and LW0 can be used to define the
position of the first pixel each line in the 32-bit long word
format or to shift the UV sequence to VU in the 16-bit YUV
formats. In case of YUV output, an odd pixel count XD
results in an incomplete pair of UV data at the end
(LW = 0) or beginning (LW = 2) of a line.
VRAM port inputs:
• VMUX, the VRAM output multiplexing signal
• VCLK to clock the FIFO register output data
• VOE to enable output data.
VRAM port outputs:
• HFL flag (half-full flag)
• INCADR (refer to Section 7.4.9)
• VRO31 to VRO0 VRAM port output data
• The reference signals for pixel and line selection on
outputs VRO7 to VRO0 (only for 24- and 16-bit video
data formats refer to Section 7.4.10).
7.4.8 VRAM PORT TRANSFER PROCEDURES
Data transfer on the VRAM port can be done
asynchronously controlled by outputs HFL, INCADR and
input VCLK (data burst transfer with bit TTR = 0).
Data transfer on the VRAM port can be done
synchronously controlled by output reference signals on
outputs VRO7 to VRO0 and a continuous VCLK of clock
rate of ¹â„₂LLC (transparent data transfer with bit TTR = 1).
In general: the scaling capability of the SAA7196 can be
used in various applications.
7.4.9 DATA BURST TRANSFER MODE
Data transfer on the VRAM port is asynchronously
(TTR = 0). This mode can be used for all output formats.
Four signals for communication with the external memory
are provided:
• HFL flag: the half-full flag of the FIFO output register is
raised when the FIFO contains at least 8 data words
(HFL = HIGH). By setting HFL = 1, the SAA7196
requests a data burst transfer by the external memory
controller, that has to start a transfer cycle within the
next 32 LLC cycles for 32-bit long word modes (16 LLC
cycles for 16- and 24-bit modes). If there are pixels in the
FIFO at the end of the line, which are not transferred, the
circuit fills up the FIFO register with ‘fill pixels’ until it is
half-full and sets the HFL flag to request a data burst
transfer. After transfer is done, HFL is used in
combination with INCADR to indicate the line
increments (see Fig.13).
• INCADR output signal is used in combination with HFL
to control horizontal and vertical address generation for
a memory controller. The pulse sequence depends on
field formats (interlace/non-interlaced or odd/even
fields, see Figs 14 and 15) and control bits
OF1 and OF0 (subaddress 20).
• VCLK input signal to clock the FIFO register output data
VRO(n). New data are placed on the VRO(n) port with
the rising edge of VCLK (see Fig.13).
• VOE input enables output data VRO(n). The outputs are
in 3-state mode at VOE = HIGH.
VOE changes only when VCLK is LOW. If VCLK pulses
are applied during VOE = HIGH, the outputs remain
inactive, but the FIFO register accepts the pulses.
1996 Nov 04
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