SAA7196 Datasheet, PDF (22/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
handbook, full pagewidth
RTCO
H/L transition
4 bits
(counter start)
HPLL
reserve
increment
128
bits 13 to 0
clock cycles ₁₃
0
22 20
FSCPLL increment
bits 22 to 0
15
10
3 bits sequence
reserve bit (1)
reserved (2)
5
10
0 48
14 19 _{time slot}
(LLC/4)
valid not valid
63 67
MHA391
(1) Sequence bit:
SECAM: 0 equals DB-line; 1 equals DR-line.
PAL: 0 equals (R − Y) line normal; 1 equals (R − Y) line inverted.
NTSC: 0 (no change).
(2) Reserve bits: 276 for 50 Hz systems; 188 for 60 Hz systems.
Fig.11 RTCO timing.
7.4 Scaler part
The scaler part receives YUV15 to YUV0 input data in
4 : 2 : 2 format.
The video data from the BCS control are processed in
horizontal direction in two separate decimation filters.
The luminance component is also processed in vertical
direction (VPU_Y).
Chrominance data are interpolated to a 4 : 4 : 4 format;
a chroma keying bit is generated. The 4 : 4 : 4 YUV data
are then converted from the YUV to the RGB domain in a
digital matrix. ROM tables in the RGB data path can be
used for anti-gamma correction of gamma-corrected input
signals. Uncorrected RGB and YUV signals can be
bypassed.
A scale control unit generates reference and gate signals
for scaling of the processed video data. After data
formatting to the various VRAM port formats, the scaled
video data are buffered in the 16 word 32-bit output FIFO
register. The scaling is performed by pixel and line
dropping at the FIFO input. The FIFO output is directly
connected to the VRAM output bus VRO31 to VRO0.
Specific reference signals support an easy memory
interfacing.
1996 Nov 04
22