SAA7196 Datasheet, PDF (55/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
QPP
TTR
EFE
pixel qualifier polarity flag
0 = PXQ is active-LOW (pin 51)
1 = PXQ is active-HIGH
transparent data transfer
0 = normal operation (VRAM data burst transfer)
1 = FIFO register transparent
extended formats enable bit (see FS bits in subaddress ‘20’)
0 = 32-bit long word output formats
1 = extended output formats (‘one pixel a time’)
Table 31 Set output field mode
BIT
OF1
OF0
0
0
0
1
1
0
1
1
MODE
both fields for interlaced storage
both fields for non-interlaced storage
odd fields only (even fields ignored)
for non-interlaced storage
even fields only (odd fields ignored)
for non-interlaced storage
Table 32 First pixel position in VRO data for FS1 = 0; FS0 = 0 (RGB) and FS1 = 0; FS0 = 1 (YUV)
LW1
0
0
1
1
LW0
0
1
0
1
31 to 24
pixel 0
pixel 0
black
black
23 to 16
pixel 0
pixel 0
black
black
15 to 8
pixel 1
pixel 1
pixel 0
pixel 0
7 to 0
pixel 1
pixel 1
pixel 0
pixel 0
CONDITIONS
EFE = 0; TTR = 0
Table 33 First pixel position in VRO data for FS1 = 1; FS0 = 1 (monochrome); note 1
LW1
0
0
1
1
0
0
1
1
LW0
0
1
0
1
0
1
0
1
31 to 24
pixel 0
black
black
black
pixel 0
black
pixel 0
black
23 to 16
pixel 1
pixel 0
black
black
pixel 1
pixel 0
pixel 1
pixel 0
15 to 8
pixel 2
pixel 1
pixel 0
black
X
X
X
X
7 to 0
pixel 3
pixel 2
pixel 1
pixel 0
X
X
X
X
CONDITIONS
EFE = 0; TTR = 0
EFE = 1; TTR = 0; LW only effects the
gray scale format
Note
1. X = don’t care.
1996 Nov 04
55