SAA7196 Datasheet, PDF (36/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
7.4.11 FIELD PROCESSING
The phase of the field sequence (odd/even dependent on
inputs HREF and VS) is detected by means of the falling
edge of VS. The current field phase is reported in the
status byte by bit OEF (see Table 14). Bit OEF can be
stable 0 or 1 for non-interlaced input frames or
non-standard input signals VS and/or HREF (nominal
condition for VS and HREF; SAA7196 with active vertical
noise limiter). A free-running odd/even flag is generated
for internal field processing if the detection reports a stable
bit OEF. Bit POE (subaddress 0B) can be used to change
the polarity of the internal flag (in case of non-standard VS
and HREF signals) to control the phase of the free-running
flag and to compensate mis-detections. Thus, the
SAA7196 can be used under various VS/HREF timing
conditions.
The SAA7196 operates on fields. To support progressive
displays and to avoid movement blurring and artifacts,
the circuit can process both or single fields of interlaced or
non-interlaced input data. Therefore the OF bits can be
used. Bits OF1 and OF0 (see Table 30) determine the
INCADR/HFL generation in ‘data burst transfer mode’.
One of the fields (odd or even) is ignored when OF1 = 1;
then no line increment sequence (INCADR/HFL) is
generated, the vertical reset pulse is only generated.
With OF1 = OF0 = 0 the circuit supports correct interlaced
data storage (see section 7.4.10.1).
7.4.12 OPERATION CYCLE
The operation is synchronized by the input field. The cycle
is specified in the flow chart (see Fig.17).
The circuit is inactive after power-on reset, VPE = 0 and
the FIFO control is set ‘empty’. The internal control
registers are updated with the falling edge of the VS signal.
The circuit is switched active and waits for a transmission
of VS and a vertical reset sequence to the memory
controller. Afterwards, the scaler waits for the beginning of
a scaling or bypass region. If the active scaling region
begins, while the bypass region is active, the bypass
region is interrupted. If a vertical sync appears, the
processing of the current line is finished. Then, the scaler
performs a coefficient update and generates a new vertical
reset (if it is still active).
Line processing starts when a line is decided to be active,
the circuit starts to scale it. Active pixels are loaded into the
FIFO register. An HFL flag is generated to initialize a data
transfer when eight words are completed. The end of a line
is reached when the programmed pixel number is
processed or when a horizontal sync pulse occurs. If there
are pixels in the FIFO register, it is filled up until it is half-full
to cause a data transfer. Horizontal increment pulses are
transmitted after this data transfer.
The scaler part will always wait for the HREF/VS pulse
before the line increment/vertical reset sequence is
performed.
After each line/field, the FIFO control is set to empty when
the increment/vertical reset pulses are transmitted.
No additional actions are necessary if the memory
controller has ignored the HFL signal. There is no need to
handle over-/underflow of the FIFO register.
7.5 Power-on reset
Power-on reset is activated at power-on or when the
supply voltage decreases below 3.5 V. The indicator
output RES is LOW for a time. The RES signal can be
applied to reset other circuits of the digital TV system.
• Bits VTRC and SSTB in subaddress ‘0DH’ are set to
zero
• All bits in subaddress ‘0EH’ are set to zero
• The FIFO register contents are undefined
• Outputs VRO, YUV, CREFB, LLCB, HREF, HS and VS
are set to 3-state
• Output INCADR = HIGH
• Output HFL = LOW until bit VPE is set to ‘1’
• Subaddress ‘30’ is set to 00H and bit VPE in subaddress
‘20H’ is set to zero (see Table 29).
1996 Nov 04
36