SAA7196 Datasheet, PDF (19/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
handbook, full pagewidth
CVBS
0
62 × 2/LLC
HSY
HSY ⁽¹⁾ +191
0
programming range
(step size: 2/LLC)
HCL
HCL ^{(1) +127}
programming range
(step size: 2/LLC)
0
216 LLC
processing delay CVBS - YUV
at YDEL = 000b
Y−output
HREF (50 Hz)
PLIN (RTS1)
(50 Hz only)
HS (50 Hz)
HS (50 Hz) ⁽²⁾
programming range
(step size: 8/LLC)
HREF (60 Hz)
HS (60 Hz)
HS (60 Hz) ⁽²⁾
programming range
(step size: 8/LLC)
768 × 2/LLC
36 × 2/LLC
+117
0
640 × 2/LLC
+97
0
burst
−64
10 × 2/LLC
−128
176 × 2/LLC
104 × 2/LLC
64 × 2/LLC
36 × 2/LLC
140 × 2/LLC
64 × 2/LLC
2 × 2/LLC
−118
−97
MHA388
Fig.8 Horizontal sync timing at HRMV = 0 and HRFS = 0 (signals HSY, HCL, HREF, PLIN and HS; 50 and 60 Hz).
1996 Nov 04
19