SAA7196 Datasheet, PDF (59/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
SYMBOL
PARAMETER
CONDITIONS
MIN.
I²C-bus, SDA and SCL (pins 3 and 4)
V_IL
LOW level input voltage
V_IH
HIGH level input voltage
I_3,4
input current
I_ACK
output current on pin 3
acknowledge
V_OL
output voltage at acknowledge I₃ = 3 mA
−0.5
3
−
3
−
Clock input timing (LLCB); see Fig.32
T_cy
cycle time
δ
duty factor
t_r
rise time
t_f
fall time
31
t_LLCBH/t_LLCB
40
−
−
Data, control and CREFB input timing; see Figs 32 and 33 and note 2
t_SU
set-up time
11
t_HD1
hold time
4
Data and control output timing; see Fig.32 and note 3
C_L
load capacitance
data, HREF and VS
15
control
7.5
t_HD2
output hold time
t_PD
propagation delay from
negative edge of LLCB
t_PZ
propagation delay from
negative edge of LLCB
(to 3-state)
C_L = 15 pF
13
data, HREF and VS;
−
C_L = 50 pF
control; C_L = 25 pF
−
note 4
−
Clock output timing (LLC, LLC2 and LLCB); see Fig.32
C_L
output load capacitance
15
t_LLC,t_LLCB cycle time
31
t_LLC2
cycle time
62
δ
duty factor
t_LLCH/t_LLC
40
t_LLC2H/t_LLC2
t_LLCBH/t_LLCB
t_r
rise time
0.6 to 2.6 V
−
t_f
fall time
2.6 to 0.6 V
−
t_dLLC2
delay between LLCB_out and
at 1.5 V, 40 pF
−
LLC2_out
Data qualifier output timing (CREFB); see Fig.32
t_HD3
output hold time
C_L = 15 pF
3
t_PD
propagation delay from positive C_L = 40 pF
−
edge of LLCB
TYP.
−
−
−
−
−
−
50
−
−
−
−
−
−
−
−
−
−
−
−
−
50
−
−
−
−
−
MAX. UNIT
+1.5
V
V_DD + 0.5 V
±10
µA
−
mA
0.4
V
45
ns
60
%
5
ns
6
ns
−
ns
−
ns
50
pF
25
pF
−
ns
29
ns
29
ns
15
ns
40
pF
45
ns
90
ns
60
%
5
ns
5
ns
8
ns
−
ns
18
ns
1996 Nov 04
59