SAA7196 Datasheet, PDF (34/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
handbook, full pagewidth ^{line n}
internal
signal
active
video
HFL
INCADR
line n + 1
horizontal blanking
last half-full request for line n
(1)
active
video
first half-full request for line n + 1
64LLC
6LLC
6LLC
minimum set-up time
64LLC
2LLC
10LLC
(1)
line increment (VRAM)
MHA395
(1) Pulse only at interlace scan.
Fig.15 Horizontal increment timing to the VRAM.
handbook, full pagewidth
line qualifier
LNQ
VS
VGT
HGT = GTH x LNQ
ACTIVE VIDEO WINDOW
LNQ
HRF
GTH
PXQ
SCALING WINDOW
field/frame
1996 Nov 04
line
MHA396
Fig.16 Reference signals for scaling window.
34