SAA7196 Datasheet, PDF (43/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
SUBADDRESS
HC6S7 to HC6S0
‘17’
HP6I7 to HP6I0
‘18’
BRIG7 to BRIG0
‘19’
DESCRIPTION
Horizontal clamp stop for 60 Hz, step size = 2/LLC. The delay time is selectable from
−254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data
7FH to 80H.
Horizontal sync start after PHI1 for 60 Hz, step size = 8/LLC. The delay time is selectable
from −32 to +31.7 µs (+97 to −97 decimal multiplier) equals data 61H to 9FH.
Forbidden, outside available central counter range, are +127 to +98 decimal multiplier equals
data 7EH to 62H as well as −98 to −128 decimal multiplier equals data 9EH to 80H.
luminance brightness control for VRAM port; see Table 28
Table 18 Aperture band-pass to select different characteristics with maximums (0.2 to 0.3 × ¹â„₂LLC); for characteristics
see Figs 19 to 28
BIT
BPSS1
0
0
1
1
BPSS0
0
1
0
1
Table 19 Coring range for high frequency components according to 8-bit luminance
BIT
CORI1
0
0
1
1
CORI0
0
1
0
1
CORING
coring off
±1 LSB of 8-bit
±2 LSB of 8-bit
±3 LSB of 8-bit
Table 20 Aperture band-pass filter weights high frequency components of luminance signal; for characteristics see
Figs 19 to 28
BIT
APER1
0
0
1
1
APER0
0
1
0
1
FACTOR
0
0.25
0.5
1
1996 Nov 04
43