SAA7196 Datasheet, PDF (52/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
8.4 Scaler part
Table 29 I²C-bus scaler control; subaddress and data bytes for writing
FUNCTION SUBADDRESS
Formats and sequence
20
Output data pixel/line⁽²⁾
21
Input data pixel/line⁽²⁾
22
Horizontal window start⁽²⁾
23
Horizontal filter
24
Output data lines/field⁽³⁾
25
Input data lines/field⁽³⁾
26
Vertical window start⁽³⁾
27
AFS/vertical Y processing
28
Vertical bypass start⁽⁴⁾
29
Vertical bypass count⁽⁴⁾
2A
2B
Chroma keying
lower limit for V
2C
upper limit for V
2D
lower limit for U
2E
upper limit for U
2F
Data path setting⁽⁵⁾
30
Unused
31
to
3F
D7
RTB
XD7
XS7
XO7
HF2
YD7
YS7
YO7
AFS
VS7
VC7
0
D6
OF1
XD6
XS6
XO6
HF1
YD6
YS6
YO6
VP1
VS6
VC6
0
D5
OF0
XD5
XS5
XO5
HF0
YD5
YS5
YO5
VP0
VS5
VC5
0
DATA
D4 D3
VPE
XD4
XS4
XO4
XO8
YD4
YS4
YO4
YO8
VS4
VC4
VS8
LW1
XD3
XS3
XO3
XS9
YD3
YS3
YO3
YS9
VS3
VC3
0
VL7
VU7
UL7
UU7
VOF
VL6
VU6
UL6
UU6
AFG
VL5
VU5
UL5
UU5
LLV
VL4
VU4
UL4
UU4
MCT
VL3
VU3
UL3
UU3
QPL
Notes
1. Default register contents to be filled in by hand.
2. Continued in ‘24’.
3. Continued in ‘28’.
4. Continued in ‘2B’.
5. Data representation, transfer mode and adaptivity.
D2
LW0
XD2
XS2
XO2
XS8
YD2
YS2
YO2
YS8
VS2
VC2
VC8
VL2
VU2
UL2
UU2
QPP
D1
FS1
XD1
XS1
XO1
XD9
YD1
YS1
YO1
YD9
VS1
VC1
0
VL1
VU1
UL1
UU1
TTR
D0
FS0
XD0
XS0
XO0
XD8
YD0
YS0
YO0
YD8
VS0
VC0
POE
VL0
VU0
UL0
UU0
EFE
DF⁽¹⁾
1996 Nov 04
52