SAA7196 Datasheet, PDF (40/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
Table 17 Function of the register bits of Table 16 for subaddresses ‘00’ to ‘19’
SUBADDRESS
IDEL7 to IDEL0
‘00’
DESCRIPTION
Increment delay time (dependent on application), step size = 4/LLC. The delay time is
selectable from −4/LLC (−1 decimal multiplier) to −1024/LLC (−256 decimal multiplier) equals
data FFH to 00H. A sign-bit, designated A08 and internally set HIGH, indicates always
negative values.
The maximum delay time in 60 Hz systems is −780 equally to 3DH; the maximum delay time
in 50 Hz systems is −944 equally to 14H.
Different processing times in the chrominance channel and the clock generation could result
in phase errors in the chrominance processing by transients in clock frequency.
HSYB7 to HSYB0
‘01’
HSYS7 to HSYS0
‘02’
HCLB7 to HCLB0
‘03’
HCLS7 to HCLS0
‘04’
HPHI7 to HPHI0
‘05’
BYPS
‘06’
PREF
‘06’
BPSS1 to BPSS0
‘06’
CORI1 to CORI0
‘06’
APER1 and APER0
‘06’
HUE7 to HUE0
‘07’
An adjustable delay (IDEL) is necessary if the processing time in the clock generation is
unknown (the horizontal PLL does not operate if the maximum delays are exceeded;
the system clock frequency is set to a value of the last update and is within ±7.1% of nominal
frequency).
Horizontal sync begin for 50 Hz, step size = 2/LLC. The delay time is selectable from
−382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) and equals data
BFH to C0H. Two’s complement numbers with ‘hidden’ sign-bit. The sign-bit is generated
internally by evaluating the MSB and the MSB-1 bits.
Horizontal sync stop for 50 Hz, step size = 2/LLC. The delay time is selectable from −382/LLC
(+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BFH to C0H. Two’s
complement numbers with ‘hidden’ sign-bit. The sign-bit is generated internally by evaluating
the MSB and the MSB-1 bits.
Horizontal clamp start for 50 Hz, step size = 2/LLC. The delay time is selectable from
−254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data
7FH to 80H.
Horizontal clamp stop for 50 Hz, step size = 2/LLC. The delay time is selectable from
−254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) equals data
7FH to 80H.
Horizontal sync start after PHI1 for 50 Hz, step size = 8/LLC. The delay time is selectable
from −32 to +31.7 µs (+118 to −118 decimal multiplier) equals data 75H to 8AH .
Forbidden, outside available central counter range, are +127 to +118 decimal multiplier
equals data 7EH to 76H as well as −119 to −128 decimal multiplier equals data 89H to 80H.
input mode select bit
0 = CVBS mode (chrominance trap active)
1 = S-Video mode (chrominance trap bypassed)
use of prefilter
0 = prefilter off (bypassed)
1 = prefilter on; PREF may be used if chrominance trap is active
Aperture band-pass to select different characteristics with maximums (0.2 to 0.3 × LLC/2);
see Table 18 and Figs 19 to 28.
Coring range for high frequency components according to 8-bit luminance; see Table 19 and
Fig.18.
Aperture band-pass filter weights high frequency components of luminance signal; see
Table 20 and Figs 19 to 28.
Hue control from +178.6° to −180.0° equals data bytes 7FH to 80H; 0° equals 00.
1996 Nov 04
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