SAA7196 Datasheet, PDF (60/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
SYMBOL
PARAMETER
CONDITIONS
Horizontal PLL
f_Hn
nominal line frequency
∆f_H/f_Hn
permissible static deviation
50 Hz system
60 Hz system
50 Hz system
60 Hz system
Subcarrier PLL
f_SCn
nominal subcarrier frequency PAL
NTSC
∆f_SC
lock-in range
PAL/NTSC
Crystal oscillator; see Fig.34 and note 5
f_n
nominal frequency
3rd harmonic
∆f_/f_n
permissible deviation f_n
temperature deviation from f_n
CRYSTAL SPECIFICATION; note 6
T_amb
C_L
R_S
C₁
C₀
temperature range
load capacitance
series resonance resistance
motional capacitance
parallel capacitance
VCLK timing; see Fig.31 and note 7
t_VCLK
t_pL, t_pH
t_r
t_f
VRAM port clock cycle time
LOW and HIGH times
rise time
fall time
note 8
note 9
VRO and reference signal output timing; see Fig.31
C_L
output load capacitance
VRO outputs
other outputs
t_HD;DAT
VRO data hold time
t_d
VRO data delay time
C_L = 10 pF; note 10
related to LCCB
(INCADR, HFL);
C_L = 10 pF; note 11
related to VCLK (HFL);
C_L = 10 pF; note 11
C_L = 40 pF; note 10
related to LCCB
(INCADR, HFL);
C_L = 25 pF; note 11
related to VCLK (HFL);
C_L = 25 pF; note 11
MIN.
TYP.
MAX. UNIT
−
15625 −
Hz
−
15734 −
Hz
−
−
±5.6
%
−
−
±6.7
%
−
−
±400
4.433618 −
3.579545 −
−
−
MHz
MHz
Hz
−
26.8
−
MHz
−
−
±50
ppm
−
−
±20
ppm
0
−
70
°C
8
−
−
pF
−
50
80
Ω
−
1.1 ±20% −
pF
−
3.5 ±20% −
pF
50
−
17
−
−
−
−
−
200
ns
−
ns
5
ns
6
ns
15
−
7.5
−
0
−
0
−
40
pF
25
pF
−
ns
−
ns
0
−
−
−
−
−
−
ns
25
ns
60
ns
−
−
60
ns
1996 Nov 04
60