SAA7196 Datasheet, PDF (12/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
7 FUNCTIONAL DESCRIPTION
7.1 Decoder part
PAL, NTSC and SECAM standard colour signals based on
line-locked clock are decoded (see Fig.27). In Y/C mode,
digitized luminance CVBS7 to CVBS0 and chrominance
CHR7 to CHR0 signals (digitized in two external ADCs)
are input. In normal mode only CVBS7 to CVBS0 is used.
The data rate is 29.5 MHz (50 MHz systems) or
24.54 MHz (60 MHz systems).
7.1.1 CHROMINANCE PROCESSOR
The input signal passes the input interface and the
chrominance band-pass filter to eliminate DC components
and is finally fed to the multiplicative inputs of a quadrature
demodulator, where two subcarrier signals (0 and 90°
phase-shifted) from a local digital oscillator (DTO1) are
applied.
The frequency is dependent on the present colour
standard. The signals are low-pass filtered and amplified
in a gain-controlled amplifier. A final low-pass stage
provides a correct bandwidth performance.
PAL signals are comb-filtered to eliminate crosstalk
between the chrominance channels according to PAL
standard requirements.
NTSC signals are comb-filtered to eliminate crosstalk from
luminance to chrominance for vertical structures.
SECAM signals are fed through a cloche filter, a phase
demodulator and a differentiator to achieve proportionality
to the instantaneous frequency. The signals are
de-multiplexed in the SECAM recombination stage after
passing a de-emphasis stage to provide the two serially
transmitted colour difference signals.
The PLL for quadrature demodulation is closed via the
cloche filter (to improve noise performance), a phase
demodulator, a burst gate accumulator, a loop filter PI1
and a discrete time oscillator DTO1. The gain control loop
is closed via the cloche filter, amplitude detector, a burst
gate accumulator and a loop filter PI2.
The sequence processor switches signals according to
standards.
7.1.2 LUMINANCE PROCESSOR
The data rate of the input signal is reduced to LLC2
frequency by a sample rate converter in the input interface.
The high frequency components are emphasized in a
prefilter to compensate for losses in the succeeding
chrominance trap. The chrominance trap is adjusted to a
centre frequency of 3.58 MHz (NTSC) or 4.4 MHz (PAL,
SECAM) to eliminate most of the colour carrier
components. The chrominance trap is bypassed for
S-VHS signals.
The high frequency components in the luminance signal
are ‘peaked’ using a band-pass filter and a coring stage.
The ‘peaked’ (high frequent) component is added to the
‘unpeaked’ signal part for sharpness improvement and
output via variable delay to the expansion bus.
7.1.3 SYNCHRONIZATION
The sync input signal is reduced in bandwidth to 1 MHz
before it is sliced and separated from the luminance signal.
The sync pulses are compared in a detector with the
divided clock signal of a counter. The resulting output
signal is fed to a loop filter that accumulates all the phase
deviations. Thereby, a discrete time oscillator DTO2 is
driven generating the line frequency control signal LFCO.
An external PLL generates the line-locked clock LLC from
the signal LFCO. A noise-limited vertical deflection pulse is
generated for vertical processing that also inserts artificial
pulses if vertical input pulses are missing. 50/60 Hz as well
as odd/even field is automatically detected by the
identification stage.
7.2 Expansion port
The expansion port is a bidirectional interface for digital
video signals YUV15 to YUV0 in 4 : 2 : 2 format (see
Table 5). External video signals can be inserted to the
scaler or decoded video signals of the decoder part can be
output.
The data direction is controlled by pin 95 (DIR = HIGH:
data from external; see Table 4).
YUV15 to YUV0, HREF, VS, LLCB and CREFB pins are
inputs when bits OECL, OEHV, OEYC of subaddress 0E
are set to ‘0’. Different modes are provided (for timing see
Figs 6 to 8):
• Mode 0: all bidirectional terminals are outputs.
The signal of the decoder part (internal YUV15 to YUV0)
is switched to be scaled.
• Mode 1: external YUV15 to YUV0 is input to the scaler.
LLCB/CREFB clock system and HREF/VS from the
SAA7196 are used to control the external source. It is
possible to switch between mode 0 and mode 1 by
means of DIR input (see Fig.5).
• Mode 2: External YUV15 to YUV0 is input to the scaler.
LLCB/ CREFB clock system and HREF/VS from
external are used.
1996 Nov 04
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