SAA7196 Datasheet, PDF (23/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
7.4.1 DECIMATION FILTERS
The decimation filters perform accurate horizontal filtering
of the input data stream.
The signal bandwidth is matched in front of the pixel
decimation stage, thus disturbing artifacts, caused by the
pixel dropping, are reduced.
The signal bandwidth can be reduced in steps of
(see Figs 29 and 30):
2-tap filter = −6 dB at 0.325 pixel rate
3-tap filter = −6 dB at 0.25 pixel rate
4-tap filter = −6 dB at 0.21 pixel rate
5-tap filter = −6 dB at 0.125 pixel rate
9-tap filter = −6 dB at 0.075 pixel rate.
The different characteristics are chosen independently by
I²C-bus control bits HF2 to HF0 when AFS = 0
(subaddress 28). In the adaptive mode with AFS = 1,
the filter characteristics are chosen dependent on the
defined sizing parameters (see Table 6).
7.4.2 VERTICAL PROCESSING (VPU_Y)
Luminance data is fed to a vertical filter consisting of a
384 × 8-bit RAM and an arithmetic block (see Fig.2).
Subsampled and interpolation operations are applied.
The luminance data is processed in vertical direction to
preserve the video information for small scaling factors
and to reduce artifacts caused by the dropping.
The available modes respectively transfer functions are
selectable by bits VP1 and VP0 (subaddress 28).
Adaptive modes, controlled by AFS and AFG bits
(subaddresses 28 and 30) are also available (see
Table 6).
Table 6 Adaptive filter selection (AFS = 1)
SCALING RATIO
XD/XS
≤1
≤14/15
≤11/15
≤7/15
≤3/15
YD/YS
≤1
≤13/15
≤4/15
FILTER FUNCTION⁽¹⁾
horizontal
bypassed
filter 1
filter 6
filter 3
filter 4
vertical
bypassed
filter 1
filter 2
Note
1. See Chapter 8.
7.4.3 RGB MATRIX
Y data and UV data are converted after interpolation into
RGB data according to CCIR601 recommendation. Data is
bypassed in 16-bit YUV formats or monochrome modes.
The matrix equations are these considering the digital
quantization:
R = Y + 1.375 V
G = Y − 0.703125 V − 0.34375 U
B = Y + 1.734375 U.
7.4.3.1 Anti-gamma ROM tables
ROM tables are implemented at the matrix output to
provide anti-gamma correction of the RGB data. A curve
for a gamma of 1.4 is implemented. The tables can be
used (bit RTB = 0, subaddress 20) to compensate gamma
correction for linear data representation of RGB output
data.
7.4.4 CHROMINANCE SIGNAL KEYER
The keyer generates an alpha signal to achieve a 5-5-5+α
RGB alpha output signal. Therefore, the processed UV
data amplitudes are compared with thresholds set via
I²C-bus (subaddresses ‘2C to 2F’). A logic ‘1’ signal is
generated if the amplitude is inside the specified amplitude
range, otherwise a logic ‘0’ is generated.
Keying can be switched off by setting the lower limit higher
than the upper limit (‘2C or 2E’ and ‘2D or 2F’).
7.4.5 SCALE CONTROL AND VERTICAL REGIONS
The scale control block SC includes address/sequence
counters to define the current position in the input field and
to address the internal VPU memories. To perform scaling,
XD of XS pixel selection in horizontal direction and YD of
YS line selection in vertical direction are applied. The pixel
and line dropping are controlled at the input of the FIFO
register.
The scaling ratio in horizontal and vertical direction is
estimated to control the decimation filter function and the
vertical data processing in the adaptive mode (AFS and
AFG bits). The input field can be divided into two vertical
regions - the bypass region and the scaling region, which
are defined via I²C-bus by the parameters VS, VC, YO and
YS.
1996 Nov 04
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