SAA7196 Datasheet, PDF (61/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
t_D
VRO disable time to 3-state C_L = 40 pF; note 12
−
−
40
ns
C_L = 25 pF; note 13
−
−
24
ns
t_E
VRO enable time from 3-state C_L = 40 pF; note 12
−
−
40
ns
C_L = 25 pF; note 13
−
−
25
ns
Response times to HFL flag
t_{HFL VOE}
HFL rising edge to VRAM port
enable
−
−
810
ns
t_{HFL VCLK} HFL rising edge to VCLK burst
−
−
840
ns
Notes
1. Levels measured with load circuits dependent on output type. Control outputs (HREF and VS excluded): 1.2 kΩ at
3 V (TTL load) and C_L = 25 pF. Data, HREF and VS outputs: 1.2 kΩ at 3 V (TTL load) and C_L = 50 pF.
2. Data input signals are CVBS7 to CVBS0, CHR7 to CHR0 (related to LLC) and YUV15 to YUV0. Control input signals
are HREF, VS and DIR.
3. Data outputs are YUV15 to YUV0. Control outputs are HREF, VS, HS, HSY, HCL, SODD, SVS, SHREF, PXQ, LNQ,
RTCO, RTS1 and RTS0.
4. The minimum propagation delay from 3-state to data active is 0 related to the falling edge of LLCB.
5. If the internal oscillator is not being used, the applied clock signal must be TTL-compatible.
6. Philips catalogue number 9922 520 30004.
7. CREFB-timing also valid for VCLK in transparent mode (see Fig.32).
8. Maximum t_VCLK = 200 ns for test mode only. The applicable maximum cycle time depends on data format, horizontal
scaling and input data rate.
9. Measured at 1.5 V level; t_pL may be infinite.
10. Timings of VRO refer to the rising edge of VCLK.
11. The timing of INCADR refers to LLCB; the rising edge of HFL always refers to LLCB. During a VRAM transfer, the
falling edge of HFL is generated by VCLK. Both edges of HFL refer to LLCB during horizontal increment and vertical
reset cycles.
12. Asynchronous signals. Its timing refers to the 1.5 V switching point of VOE input signal (pin 53).
13. The timing refers to the 1.5 V switching point of VMUX signal (pin 46) in 32- to 16-bit multiplexing mode.
Corresponding pairs of VRO outputs are together connected.
1996 Nov 04
61