SAA7196 Datasheet, PDF(38/76 Page) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

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SAA7196 Datasheet, PDF (38/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

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Philips Semiconductors

Digital video decoder, Scaler and Clock

generator circuit (DESCPro)

Product speciï¬cation

SAA7196

8.2 I2C-bus status information

Table 14 I2C-bus status byte (X in address byte = 1; 41H at I2CSA = LOW or 43H at I2CSA = HIGH); see Table 15

FUNCTION

Status byte 0 (transmitted after

RES = 0 or at SSTB = 0)

Status byte 1 (transmitted at

SSTB = 1)

ID3

ID2

ID1

STTC HLCK FIDT

DATA

ID0

DIR

OEF SVP

ALTD CODE

Table 15 Function of status bits; note 1

BIT

DIR

OEF

SVP

STTC

HLCK

FIDT

ALTD

CODE

FUNCTION

state of input DIR (pin 95): direction control of expansion port YUV

DIR = 0: the scaler uses internal source (decoder output)

DIR = 1: the scaler uses external data of expansion bus

identiï¬cation of ï¬eld sequence dependent on HREF and VS

0 = even field detected

1 = odd field detected

state of VRAM port (state of, bit VPE cleared by RES)

0 = inputs HFL and INCADR inactive

1 = inputs HFL and INCADR active

horizontal time constant information (for future application with logical comb-ï¬lter only)

0 = TV time constant (slow)

1 = VCR time constant (fast)

horizontal PLL information

0 = HPLL locked

1 = HPLL unlocked

ï¬eld information

0 = 50 Hz system detected

1 = 60 Hz system detected

line alternation

0 = no line alternating colour burst detected

1 = line alternating colour burst detected (PAL or SECAM)

colour information

0 = no colour detected

1 = colour detected

for future enhancements, do not evaluate

Note

1. Software model of SAA7196 compatible with ID3 to ID0 = 0; version V0 (first version).

1996 Nov 04

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