SAA7196 Datasheet, PDF (33/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
handbook, full^Pp^Ia^Xge^Cw^Lid^Kth
1/2LLC
FIFO
memory
7
filling level
HFL
VCLK
VOE
8
9
8
87 6
65
4
4
note 1
note 2
note 3
VRO(n)
70
12
3
45
6
7
MHA393
(1) Minimum 8 words available in FIFO.
(2) Maximum 32LLC (16PIXCLK).
(3) 1 transfer cycle (8 VCLK cycles).
Fig.13 Output port transfer to VRAM at 32-bit data format without scaling. If VCLK cycles occur at VOE = HIGH,
the FIFO register is unchanged, but the outputs VRO31 to VRO0 remain in 3-state position.
handbook, full pagewidth
line n
internal
signal
active
video
line n + 1
vertical blanking
last half-full request for line n
(1)
HFL
64LLC
64LLC
min. set-up time
INCADR
10LLC
(1)
line increment seqence
vertical reset pulse
(1) Only available for interlaced processing at the beginning of an odd field.
Fig.14 Vertical reset timing to the VRAM.
1996 Nov 04
33
MHA394