SAA7196 Datasheet, PDF (69/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
SUBADDRESS
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
BITS
XO7 to XO0
HF2 to HF0, XO8,
XS8 and XS9,
XD8 and XD9
YD7 to YD0
YS7 to YS0
YO7 to YO0
AFS, VP1 and VP0, YO8,
YS8 and YS9,
YD8 and YD9
VS7 to VS0
VC7 to VC0
VS8,VC8, POE
VL7 to VL0
VU7 to VU0
UL7 to UL0
UU7 to UU0
VOF, AFG
FUNCTION
LSBs for horizontal window start position
horizontal filter select and MSBs of
subaddresses 21, 22, 32
LSBs output lines/field
LSBs input lines/field
LSBs vertical window start position
MSBs of subaddresses 25, 26, 27
LSBs vertical bypass start position
LSBs vertical bypass lines/field
MSBs of subaddresses 29, 2A and
odd/even polarity switch
chroma key: lower limit V (R−Y)
chroma key: upper limit V (R−Y)
chroma key: lower limit U (B−Y)
chroma key: upper limit U (B−Y)
VRAM port MUX enable, adaptively
VALUE (HEX)
03⁽⁹⁾; 00⁽¹⁰⁾
85⁽⁹⁾; 8F⁽¹⁰⁾
90⁽⁹⁾; FF⁽¹⁰⁾
90⁽⁹⁾; FF⁽¹⁰⁾
03⁽⁹⁾; 00⁽¹⁰⁾
00⁽⁹⁾; 0F⁽¹⁰⁾
00⁽¹¹⁾
00⁽¹¹⁾
00⁽¹¹⁾
00
FF⁽¹²⁾
00
00
80⁽¹³⁾
Notes
1. Dependent on application (Figs 35 and 36).
2. For QUAM standards.
3. HPLL is in TV-mode, value for VCR-mode is 84H (85H for SECAM VCR-mode).
4. For SECAM.
5. For Y/C-mode.
6. Nominal value for UV-CCIR-level with NTSC source.
7. Nominal value for UV-CCIR-level with PAL source.
8. ROM-table is active, scaler processes both fields for interlaced display; VRAM port enabled; long word position = 0;
16-bit 4 : 2 : 2 YUV output format selected.
9. Scaler processes a segment of (384 pixels × 144 lines) with defaults XO and YO set to the first valid pixel/line and
line/field (for decoder as input source) with scaler factors of 1 : 1; horizontal and vertical filters are bypassed, filter
select adaptability is disabled.
10. If no scaling and panning is wanted, the parameters XD, XS, YD and YS should be set to maximum (3FFH) and the
parameters XO and YO should be set to minimum (000H). In this case, the HREF and VS signals define the
processing window of the scaler.
11. No vertical bypass region is defined.
12. Chrominance keyer is disabled (VL = 0, VU = −1).
13. 32-bit to 16 VRAM port MUX, adaptive scale and Y-limiter are disabled; pixel and line qualifier polarity for transparent
mode are set to zero (active); data burst transfer for the 32-bit long word formats is set.
1996 Nov 04
69