SAA7196 Datasheet, PDF (14/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
7.3 Monitor controls BCS
7.3.1 BRIGHTNESS AND CONTRAST CONTROLS
The luminance signal can be controlled via I²C-bus
(see Table 16) by the bits BRIG7 to BRIG0 and
CONT6 to CONT0.
Table 1 Brightness control
BRIGHTNESS
CONTROL
00H
80H
FFH
VALUE
minimum offset
CCIR level
maximum offset
Table 2 Contrast control
CONTRAST
CONTROL
00H
40H
7FH
VALUE
luminance off
CCIR level
1.9999 amplitude
7.3.2 SATURATION CONTROL
The chrominance signal can be controlled via I²C-bus (see
Table 16) by the bits SAT6 to SAT0 and HUE7 to HUE0.
Table 3 Saturation control
SATURATION
CONTROL
00H
40H
7FH
VALUE
colour off
CCIR level
1.9999 amplitude
Clipping: all resulting output values are clipped to
minimum (equals 1) and maximum (equals 254).
Table 4 Operation modes; notes 1 to 3
MODE
OEYC
I²C BIT
OEHV
OECL
0
1
1
1
1
X
1
1
2
X
0
0
3
X
0
1
Notes
1. X = don’t care.
2. I = input to monitor control/scaler.
3. O = output from decoder.
DIR
PIN 95
LOW
HIGH
HIGH
HIGH
YUV
O
I
I
I
INPUT SOURCE
HREF
VS
LLCB
O
O
O
O
O
O
I
I
I
I
I
O
CREFB
O
O
I
O
1996 Nov 04
14