SAA7196 Datasheet, PDF (56/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
Table 34 FIFO output register format select (bit EFE; see ‘30’)
EFE
FS1
FS0
OUTPUT FORMAT (Tables 8 to 11)
0
0
0
RGB 5-5-5+α; 2 × 16-bit/pixel; 32-bit word length; RGB matrix on,
VRAM output format
0
0
1
YUV 4 : 2 : 2; 2 × 16-bit/pixel; 32-bit word length; RGB matrix off,
VRAM output format
0
1
0
YUV 4 : 2 : 2; 1 × 16-bit/pixel; 16-bit word length; RGB matrix off,
optional output format
0
1
1
monochrome mode; 4 × 8-bit/pixel; 32-bit word length; RGB matrix off,
VRAM output format
1
0
0
RGB 5-5-5+α; 1 × 16-bit/pixel; 16-bit word length; RGB matrix on,
VRAM output + transparent format
1
0
1
YUV 4 : 2 : 2+α; 1 × 16-bit/pixel; 16-bit word length; RGB matrix off,
VRAM output + transparent format
1
1
0
RGB 8-8-8+α; 1 × 24-bit/pixel; 24-bit word length; RGB matrix on,
VRAM output + transparent format
1
1
1
monochrome mode; 2 × 8-bit/pixel; 16-bit word length; RGB matrix off,
VRAM output + transparent format
Table 35 Horizontal decimation filter
HF2
HF1
HF0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TAPS
2
3
5
9
1
1
8
4
FILTER (see Figs 29 and 30)
filter 1
filter 2
filter 3
filter 4
filter bypassed
filter bypassed + delay in Y channel of 1T
filter 5
filter 6
Table 36 Vertical luminance data processing
VP1
VP0
PROCESSING (APPROXIMATE EQUATIONS)
0
0
bypassed
0
1
delay of one line H(z) = z^−H
1
0
vertical filter 1: [H(z) = ¹â„₂(1 + z^−H)]
1
1
vertical filter 2: [H(z) = ¹â„₄(1 + 2z^−H + z^−2H)]
1996 Nov 04
56