SAA7196 Datasheet, PDF (42/76 Pages) NXP Semiconductors – Digital video decoder, Scaler and Clock generator circuit DESCPro

Philips Semiconductors
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
Product specification
SAA7196
SUBADDRESS
DESCRIPTION
CHRS
‘0E’
S-VHS bit (chrominance from CVBS or from chrominance input)
0 = controlled by bit BYPS (subaddress 06)
1 = chrominance from chrominance input CHR7 to CHR0
GPSW2 and GPSW1 general purpose switches; see Table 22
‘0E’
AUFD
‘0F’
automatic field detection
0 = field selection by bit FSEL
1 = automatic field detection by SAA7196
FSEL
‘0F’
field select (bit AUFD = 0)
0 = 50 Hz (625 lines)
1 = 60 Hz (525 lines)
SXCR
‘0F’
SECAM cross-colour reduction
0 = reduction off
1 = reduction on
SCEN
‘0F’
enable sync and clamping pulse
0 = HSY and HCL outputs HIGH (pins 25 and 26)
1 = HSY and HCL outputs active
YDEL2 to YDEL0
‘0F’
luminance delay compensation; see Table 23
HRFS
‘10’
select HREF position
0 = normal, HREF is matched to YUV output on expansion port
1 = HREF is matched to CVBS input port
VNOI1 to VNOI0
‘10’
vertical noise reduction; see Table 24
CHCV7 to CHCV0
‘11’
chrominance gain control (nominal values) for QAM-modulated input signals, effects UV
output amplitude (SECAM with fixed gain); see Table 25
SATN6 to SATN0
‘12’
chrominance saturation control for VRAM port; see Table 26
CONT6 to CONT0
‘13’
luminance contrast control for VRAM port; see Table 27
HS6B7 to HS6B0
‘14’
Horizontal sync begin for 60 Hz, step size = 2/LLC. The delay time is selectable from
−382/LLC (+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data
BFH to C0H. Two’s complement numbers with ‘hidden’ sign-bit. The sign-bit is generated
internally by evaluating the MSB and the MSB-1 bits.
HS6S7 to HS6S0
‘15’
Horizontal sync stop for 60 Hz, step size = 2/LLC. The delay time is selectable from −382/LLC
(+191 decimal multiplier) to +128/LLC (−64 decimal multiplier) equals data BFH to C0H. Two’s
complement numbers with ‘hidden’ sign-bit. The sign-bit is generated internally by evaluating
the MSB and the MSB-1 bits.
HC6B7 to HC6B0
‘16’
Horizontal clamp begin for 60 Hz, step size = 2/LLC. The delay time is selectable from
−254/LLC (+127 decimal multiplier) to +256/LLC (−128 decimal multiplier) and equals data
7FH to 80H.
1996 Nov 04
42