CS4210 Datasheet, PDF (97/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

5.0 Electrical Specifications
This section provides information on NAND tree test mode,
absolute maximum ratings, recommended operating condi-
tions, and DC/AC characteristics for the Geode CS4210.
5.1 NAND TREE TEST MODE
The NAND tree test mode is used to test input and bidirec-
tional pins which are part of the NAND tree chain. After
power is applied to the CS4210, pin 7 (TESTO) is the out-
put of the NAND tree. To test the NAND tree, all inputs in
Table 5-1 are held low and then a high is successively
applied to the inputs in the order listed in Table 5-1. The
TESTO output will toggle on each input change as shown
in Figure 5-1.
The TESTO pin will continue to output the result of the
NAND tree during normal operation. If this is undesirable,
nscControl.testOutSel (BAR1+Offset 00h[19]) can be set
and TESTO will reflect the BIST output which does not tog-
gle during normal operation. The nscControl register is
loaded via the serial EEPROM upon power up, so nscCon-
trol.testOutSel can be set as the default if desired.
Signal Name
LNKON
SCLK
CTL0
CTL1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DIRECT
CCLKI
TESTEN#
AD0
AD1
Pin No.
98
95
93
92
90
89
88
86
85
84
82
81
79
78
76
74
73
Table 5-1. NAND Tree Test Mode Pins
Signal Name
AD2
AD3
AD4
AD5
AD6
AD7
C/BE0#
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
C/BE1#
PAR
Pin No.
72
71
69
68
67
66
65
64
62
61
59
58
57
56
54
53
52
Signal Name
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
C/BE2#
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
IDSEL
Pin No.
51
49
48
47
45
44
43
41
40
38
37
36
34
33
32
31
29
Signal Name
C/BE3#
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PME#
PGNT#
PCLK
RST#
EEDATA
EECLK
Pin No.
28
27
26
25
23
22
21
19
18
17
14
12
10
5
4
TESTO
LNKON
100 ns
SCLK
CTL0
CTL1
DATA0
:::
:::
:::
EECLK
Note: The following pins are not in the NAND tree: CMC, CMCL, INTA#, PREQ#, CCLKO, LREQ, LPS, and all supplies.
Figure 5-1. NAND Tree Output Waveform
Revision 1.0
97
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