CS4210 Datasheet, PDF (33/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

4.0 Register Descriptions
The registers of the CS4210 can broadly be divided into
two categories:
1) OHCI Configuration Registers
2) National (Vendor) Specific Configuration Registers
Both are memory mapped offsets accessed via Base
Address Registers (BARs) specified in the PCI Configura-
tion Space Header.
The remaining sub-sections of this chapter are as follows:
• A brief discussion on how to access the registers
located in the PCI Configuration Space
• Register Summary
• Detailed bit formats of all registers
4.1 PCI CONFIGURATION SPACE ACCESS
A PCI configuration read or write cycle is accomplished by
writing the bus, function, device, and register number into
the 32-bit index register at 0CF8h, then performing a corre-
sponding PCI configuration read or write of the 32-bit data
register at 0CFCh. The format of the value written to
0CF8h (PCI_INDEX) is shown in Table 4-1.
The CS4210 provides a configuration space, whose first
40h bytes adhere to the format outlined in Revision 2.1 of
the document entitled, “PCI Local Bus Specification”. This
is a Type 0 header. This configuration space header con-
tains two 32-bit BARs that specify memory space usage.
The first BAR contains the memory address of the OHCI
defined registers. The second BAR contains the memory
address of the National Semiconductor defined registers.
31
30
24
Configuration
Space Mapping
1 (Enable)
RSVD
000 000
Table 4-1. PCI Index Register (0CF8h)
23
16 15
11 10
8
Bus
Number
0000 0000
Device
Number
xxxx x
Function
Number
xxx
7
2
Register
Number
xxxx xx
1
0
00
00 (Always)
Revision 1.0
33
www.national.com