CS4210 Datasheet, PDF (42/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
Table 4-6. PCI Configuration Register Definitions
Bit
Name
Access Reset Description
Index 00h
Vendor Identification Register
15:0
Vendor ID
RO
1000h Vendor Identification: This register identifies the manufacturer of the
CS4210 as National Semiconductor.
Index 02h
Device Identification Register
15:0
Device ID
RO
000Fh Device Identification: This register identifies the CS4210 as the IEEE
1394 Open Host Controller.
Index 04h
PCI Command Register
This register provides coarse control over the device’s ability to generate and respond to PCI cycles. It is required that the CS4210 sup-
port both PCI bus-mastering and memory-mapping of all configuration and operational registers into the memory address space of the
PC host. Consequently, the fields memoryAccess and masterEn should always be set to 1 during device configuration.
Once the CS4210 starts processing DMA descriptor lists, the action of resetting either field memoryAccess or masterEn to 0 halts all
PCI operations. If the field memoryAccess is reset to 0, the CS4210 can no longer respond to any software command addressed to it
and interrupt generation is halted.
15:10
9
8
7
6
5
4
RSVD
fastBBEn
systemErrEn
waitCycEn
parityErrResp
VGAPalSnoop
memWrInvalid
3
specCycRec
2
masterEn
1
memoryAccess
0
ioAccess
---
000000 Reserved
RO
0
Fast Back-to-Back Enable: This function is not supported and is always
disabled. 0 = Disable; 1 = Enable.
R/W
0
System Error Enable: Allow assertion on detection of special errors. 0 =
Disable; 1 = Enable.
RO
0
Wait Cycle Control: This function is not supported and is always disabled.
0 = Disable; 1 = Enable.
R/W
0
Parity Error Response: Allow the CS4210 to drive PERR# when a parity
error is detected. 0 = Disable; 1 = Enable.
RO
0
VGA Palette Snoop: This function is not supported, Is is always disabled. 0
= Disable; 1 = Enable.
RO
0
Memory Write and Invalidate: Allow the CS4210 to do memory write and
invalidate cycles. 0 = Disable; 1 = Enable.
If disabled, memory write commands must be used.
RO
0
Special Cycles: This function is not supported and is always disabled. 0 =
Disable; 1 = Enable.
R/W
0
Bus Master: Allow the CS4210 bus mastering capabilities.
0 = Disable; 1 = Enable.
R/W
0
Memory Space Access: Allow the CS4210 to respond to memory cycles
from the PCI bus. 0 = Disable; 1 = Enable.
This bit must be set to 1 to access memory offsets through BAR0 (Index
10h) and BAR1 (Index 14h).
RO
0
I/O Space Access: Allow the CS4210 to respond to I/O cycles from the PCI
bus. 0 = Disable; 1 = Enable.
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