CS4210 Datasheet, PDF (92/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
Table 4-57. BAR1+Offset 00h: nscControl Register (Continued)
Bit
Name
Access Reset Description
3
wpDisable
RW
0
Write Protect Disable: Turn-off write protection of selected vendor specific
registers. 0 = Disable; 1 = Enable.
2
atresBackoff
RW
0
AT Response Context Backoff: Allow backoff timing for retransmission of
asynchronous requests via the AT response context.
0 = Disable; 1 = Enable.
1
atreqBackoff
RW
0
AT Request Context Backoff: Allow backoff timing for retransmission of
asynchronous requests via the AT request context. 0 = Disable; 1 = Enable.
0
shortCycle
RW
0
Short Cycle: Allow cycle count to increment when cycle offset = 511
instead of 3071. 0 = Disable; 1 = Enable.
Short cycle operation is intended for testing only.
The altMode bits provide fine control over the individual
P1394a features. The individual bit controls for altIdleIn-
sert, altMultiSpd, altAckAccel, and altAckConcat can be
modified by controlling the altMode bits. These four indi-
vidual bits are considered the modifier in the Table 4-57.
The combination of the individual alt bits and the altMode
determine the enabling of the P1394a feature. For exam-
ple, the second line in the table represents the case where
P1394a features are enables with no modification. The
result field being one indicates that the P1394a feature is
enabled. For the case of the fourth row, if the altAckAccel
bit were set to one for example, then that single P1394a
feature would be disabled as indicated by the zero in the
result column.
nscControl.altMode
(BAR1+Offset 00h[17:16]
00 or 11 (XOR)
00 or 11
00 or 11
00 or 11
01 (AND)
01
01
01
10 (OR)
10
10
10
Table 4-58. altMode
HCControl.aPhyEnhance
Enable
(BAR0+Offset 50h[22])
nscControl.Modifier
(BAR1+Offset 00h[9, 7, 6, 5])
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
Result
0
1
1
0
0
0
0
1
0
1
1
1
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