CS4210 Datasheet, PDF (46/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
Table 4-6. PCI Configuration Register Definitions
Bit
Name
Access Reset Description
Index 46h-47h
Power Management Capabilities Register
This register specifies capabilities related to PCI power management. This register is available only if the PCICapabilities bit (BAR1 Off-
set 00h[20]) is set in the nscControl register.
15:11
pmeSupport
RO
01000 Power Management Event Support: Bit 14 is one indicating PME# may
be asserted from the D3HOT power state. PME# is not capable of asserting
from other states.
10
d2Support
RO
0
D2 Power State Support: This bit reads zero indicating that the D2 power
state is not supported.
9
d1Support
RO
0
D1 Power State Support: This bit reads zero indicating that the D1 power
state is not supported.
8
dynData
RO
0
Dynamic Power Consumption Data: This bit reads zero indicating that
dynamic power consumption data is not provided.
7:6
RSVD
RO
0
Reserved
5
DSI
RO
0
Driver Special Initialization: This bit reads zero indicating that no special
initialization is required beyond the standard PCI configuration header
before a generic class driver is able to use the CS4210.
4
auxPower
RO
0
Auxiliary Power: This bit reads zero indicating that PME# generation in the
D3COLD state is not supported.
3
pmeCLK
RO
0
Power Management Event Clock: This bit reads zero indicating that no
host bus clock is required to generate PME#.
2:0
pmVerson
RO
000 Power Management Version: This field reads zero indicating compatibility
with the PCI Bus Power Interface Management Specification previous to
revision 1.0.
Note:
The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be con-
figured by serial EEPROM. If enabled in the EEPROM the reset value of this register is 4000h. If not or if no EEPROM is
present, then the reset value is 000h.
Index 48h
Power Management and Control Status Register
This register implements the control and status of the PCI power management function. This register is available only if the PCICapabil-
ities bit (BAR1 Offset 00h[20]) is set in the nscControl register.
15
pmeStatus
RC
1
Power Management Event Status: This bit is set when PME# is asserted.
Write 1 to clear. The PME# signal is also cleared when this is bit is written
to 1. A write of zero has no effect.
14:9
dynData
RO
000000 Dynamic Power Consumption Data: This field reads 0 indicating that
dynamic data is not reported.
8
pmeEnab
R/W
0
Power Management Event Enable: When set, this bit enables the asser-
tion of PME#.
7:5
RSVD
---
000 Reserved
4
dynDataEnab
RO
Dynamic Power Consumption Data: This bit reads 0 indicating that
dynamic data is not reported.
3:2
RSVD
---
00
Reserved
1:0
pwrState
R/W
Power State: This field is used to determine and set the CS4210 power
state.
00 = Current power state is D0
01 = Current power state is D1
10 = Current power state is D2
11 = Current power state is D3hot
Since D1 and D2 are not supported, a write of either 01 or 10 is treated as
the D0 state.
Note:
The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be con-
figured by serial EEPROM. If enabled in the EEPROM the reset value of this register is 8000h. If not or if no EEPROM is
present then the reset value is 000h.
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Revision 1.0