CS4210 Datasheet, PDF (25/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Operational Description (Continued)
3.5.4 Retries
For asynchronous receive, the CS4210 supports dual-
phase retry for packets that must be busied. For asynchro-
nous transmit, CS4210 supports the single-phase retry
protocol. The retry mechanism is managed by hardware
and invisible to software.
3.5.5 DMA Summary
Table 3-9 is a summary of DMA information for reference
purposes.
DMA
Asynchronous
Transmit
Contexts
1
Request
Per Context
Registers
ContextControl
CommandPtr
Asynchronous
Receive
Isochronous
Transmit
1
Response
1
Request
1
Response
8
ContextControl
CommandPtr
ContextControl
CommandPtr
ContextControl
CommandPtr
ContextControl
CommandPtr
Isochronous
Receive
Self-ID
8
ContextControl
CommandPtr
ContextMatch
1
SelfIDBuffer
SelfIDCount
Table 3-9. DMA Summary
Per Context
Interrupts
reqTxComplete
respTxComplete
Receive
Mode
DMA Commands
OUTPUT_MORE
OUTPUT_MORE-Immediate
OUTPUT_LAST
OUTPUT_LAST-Immediate
ARRQ RQPkt
Buffer-fill
INPUT_MORE
ARRS RSPkt
IsochTx
IsochTxIntEventn
IsochTxIntMaskn
IsochRx
IsochRxIntEventn
IsochRxIntMaskn
SelfIDComplete
Packet-per-
buffer
Buffer-fill
Buffer-fill
OUTPUT_MORE
OUTPUT_MORE-Immediate
OUTPUT_LAST
OUTPUT_LAST-Immediate
STORE_VALUE
INPUT_MORE INPUT_LAST
INPUT_MORE
Z tcodes
2-8 0, 1, 4,
5, 9, A,
E
2, 6, 7,
B
1 0, 1, 4,
5, 9, E*
2, 6, 7,
B
1-8 A
1-8 A
1
N/A
Revision 1.0
25
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