CS4210 Datasheet, PDF (7/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Architectural Description (Continued)
1.2.1 Transfer Engine
The transfer engine performs data movement between dif-
ferent sources/sinks:
1) Host memory (TxFIFOs/RxFIFO, Scratchpad SRAM)
2) DMA modules (ATDMA, ITDMA, or RDMA)
All byte alignment and byte swapping tasks are also per-
formed by the transfer engine.
1.2.2 Host Memory Organization
The 1394 OHCI specification allows for many different data
FIFO implementations. This CS4210 implements two trans-
mit FIFOs (asynchronous and isochronous) and a single
receive FIFO. The transmit FIFOs share a single embed-
ded dual-port SRAM (36x1024). The receive FIFO uses a
single embedded dual-port SRAM (36x1024). A small
transmit FIFO is also implemented using latches and some
decoding logic.
All FIFOs may be tested using an embedded RAM BIST
controller. See Section 4.5.4 "nscRAMBist" on page 94 for
more details.
1.2.3 ATDMA
The ATDMA module controls the transmission of all asyn-
chronous packets. This includes AT (Asynchronous Trans-
mit) Request context packets, AT Response context
packets and all physical DMA transmit request and
response packets. The ATDMA module also controls
retransmission of packets as required by the OHCI specifi-
cation.
1.2.4 ITDMA
The ITDMA module controls the transmission of all isochro-
nous packets. Annex E of the OHCI specification describes
the operation of the ITDMA module. This annex was con-
tributed by National Semiconductor.
1.2.5 RDMA
The RDMA module processes all received packets and
transmit status. This includes packets destined for the AR
(Asynchronous Receive) Request context, AR Response
context, all IR (Isochronous Receive) contexts, the Self-ID
buffer, and all physical DMA requests (including CSR
accesses). It also examines the transmit status to manage
the collection of currently active physical DMA requests.
1.3 TRANSMIT DRAIN
The transmit drain module accepts packets from the
TxFIFOs (asynchronous and isochronous) and interfaces
with the link layer module to transmit these packets. It also
places transmit completion status in the TxFIFO.
1.4 RECEIVE FILL
The receive fill module accepts packets from the link layer
and places them into the RxFIFO. It performs packet filter-
ing and routing. It also determines which handshake, if any,
to return for each received packet.
1.5 LINK LAYER
The link layer module implements a 1394 link layer function
developed for this host controller application. It includes
support for the CRC32 generation/checking, link state
machine, transmit/receive data paths and the generation/
reception of cycle start packets. This module includes sup-
port for features defined in the P1394a supplement.
1.6 PHYSICAL LAYER INTERFACE
The physical layer interface module implements the exter-
nal interface to connect to the Geode CS4103 P1394a
physical layer device. It includes support for features
defined in revision 2.0 of the P1394a specification.
1.7 REGISTER SET
The register set module coordinates slave accesses to the
host controller registers. It fields read/write requests from
the PCI interface module. It can also read configuration
data from a serial EEPROM device via an I²C interface.
1.8 RELATED DOCUMENTS
The following documents may be useful in understanding
the terms and concepts used in this publication.
• 1394 Open Host Controller Interface Specification
Release 1.0
• IEEE 1394-1995 High Performance Serial Bus, 1995
• ISO/IEC 13213:1994 Control and Status Register Archi-
tecture for Microcomputer Buses International Stan-
dards Organization, 1994
• IEEE P1394a Standard for a High Performance Serial
bus (Supplement)
Revision 1.0
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