CS4210 Datasheet, PDF (94/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

Register Descriptions (Continued)
4.5.4 nscRAMBist
The nscRAMBist register (Table 4-61) is used to test the
FIFOs implemented in SRAM. The bistGo bit is set and the
bistFail and bistPass bits are polled until one is set, indicat-
ing pass or fail. The CS4210 must be reset before normal
operation can resume.
4.5.5 nscCmcControl
The nscCmcControl register (Table 4-62) controls the state
of the CMC and CMCL pins. These pins are intended for
use with Contender pins on 1394-1995 PHY devices. This
feature is not used on the CS4103.
4.5.6 nscTxThreshold
The nscTxThreshold register (Table 4-63) is used to control
the point at which the transmit FIFOs start sending data
over the 1394 bus. Lowering the threshold value causes
smaller packets to be sent. This register can only be written
to when the nscControl.wpDisable bit (BAR1+Offset
00h[3]) is set. This register may be configured via the serial
EEPROM interface (if EEPROM is present).
4.5.7 nscSubSystem
The nscSubSystem register (Table 4-64) is used to config-
ure the subsystem vendor ID and the subsystem device ID
values in the PCI configuration space. This register can
only be written to when the nscControl.wpDisable bit
(BAR1+Offset 00h[3]) is set. This register may be config-
ured via the serial EEPROM interface (if EEPROM is
present).
Bit
31:10
9
8
7:1
0
Name
RSVD
bistFail
bistPass
RSVD
bistGo
Table 4-61. BAR1+Offset 14h: nscRAMBist Register
Access Reset Description
--
0
Reserved
RU
Undef Built-in Self-Test Fail: Set to 1 when RAM BIST has failed.
RU
Undef Built-in Self-Test Pass: Set to 1 when RAM BIST has passed.
--
0
Reserved
RW
Undef Built-in Self-Test Go: RAM BIST is started by writing a 1 to this bit.
Table 4-62. BAR1+Offset 18h: nscCmcControl Register
Bit
31:2
1
0
Name
RSVD
CMCL
CMC
Access
--
RW
RW
Reset
0
0
0
Description
Reserved
Contender Master Control Link Enabled: This bit is ANDed with HCCon-
trol.LinkEnable (BAR0+Offset 50h[17]) and the result is reflected on pin 3.
Contender Master Control: Selects polarity of CMC output. This bit is
directly reflected on pin 2. 0 = Low; 1 = High.
Bit
31:16
15:0
.
Bit
31:16
15:0
Table 4-63. BAR1+Offset 20h: nscTxThreshold Register
Name
isochTxThrsh
asyncTxThrsh
Access
RW
RU
Reset
01FEh
01FEh
Description
Isochronous Transmit Threshold: FIFO threshold value when transmit-
ting isochronous packets. D[18:16] are hardwired to 110 and D[31:25] are
hardwired to 00h.
Asynchronous Transmit Threshold: FIFO threshold value when transmit-
ting asynchronous packets. D[2:0] are hardwired to 110 and the D[15:9] are
hardwired to 00h.
Name
deviceID
vendorID
Table 4-64. BAR1+Offset 24h: nscSubSystem Register
Access
RW
RW
Reset
0000h
0000h
Description
Device ID: PCI configuration subsystem device ID.
Vendor ID: PCI configuration subsystem vendor ID.
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