CS4210 Datasheet, PDF (15/102 Pages) National Semiconductor (TI) – IEEE 1394 OHCI Controller

3.0 Operational Description
3.1 OVERVIEW
The CS4210 is an implementation of the link layer protocol
of the 1394 serial bus, with additional features to support
the transaction and bus management layers. The CS4210
also includes DMA engines for high-performance data
transfer and a PCI host bus interface. IEEE 1394 serial bus
(and 1394 OpenHCI) protocols support two types of data
transfer: asynchronous and isochronous.
• Asynchronous data transfer puts the emphasis on guar-
anteed delivery of data, with less emphasis on guaran-
teed timing.
• Isochronous data transfer is the opposite, with the
emphasis on the guaranteed timing of the data, and less
emphasis on delivery.
3.1.1 Asynchronous Data Transfer Functions
The CS4210 can transmit and receive all of the defined
1394 packet formats. Packets to be transmitted are read
out of host memory and received packets are written into
host memory, both using DMA. The CS4210 can also be
programmed to act as a bus bridge between the host bus
and 1394 devices by directly executing 1394 read and write
requests as reads and writes to the host bus memory
space.
3.1.2 Isochronous Data Transfer Functions
The CS4210 is capable of performing the cycle master
function as defined by the IEEE 1394 OHCI specification.
This means it contains a cycle timer and counter, and can
queue the transmission of a special packet called a “cycle
start” after every rising edge of the 8 kHz cycle clock. The
CS4210 can generate the cycle clock internally or use an
external reference connected to the CCLKI input (pin 78).
When not the cycle master, the CS4210 keeps its internal
cycle timer synchronized with the cycle master node by
correcting its own cycle timer with the reload value from the
cycle start packet. Conceptually, the CS4210 supports one
DMA controller each for isochronous transmit and isochro-
nous receive. The CS4210 provides eight isochronous
transmit contexts. The isochronous transmit DMA controller
can transmit from each context during each cycle. Each
context can transmit data for a single isochronous channel.
The CS4210 provides eight isochronous receive contexts.
The isochronous receive DMA controller can receive data
for each context during each cycle. Each context can be
configured to receive data from a single isochronous chan-
nel. Additionally, one context can be configured to receive
data from multiple isochronous channels (see bit 28, multi-
ChanMode, in Table 4-53 on page 87 for programming
details).
3.1.3 Miscellaneous Functions
Upon detecting a bus reset, the CS4210 automatically
flushes all packets queued for asynchronous transmission.
Asynchronous packet reception continues without interrup-
tion, and a token appears in the received request packet
stream to indicate the occurrence of the bus reset. When
the CS4103 provides the new local node ID, the CS4210
loads this value into its Node ID register, see Table 3-1.
Asynchronous packet transmit will not resume until
directed to by software. Because target node ID values
may have changed during the bus reset, software will not
generally be able to re-issue old asynchronous requests
until software has determined the new target node IDs. Iso-
chronous transmit and receive functions are not halted by a
bus reset, instead they restart as soon as the bus initializa-
tion process is complete. A number of management func-
tions are also implemented by the CS4210. A global unique
ID register, shown in Table 3-2, can only be written once.
For full compliance with higher level standards, this register
must be written before the boot block is read. To make this
implementation simpler, the CS4210 has an interface to an
external serial I²C EEPROM such as the Fairchild Semi-
conductor NM24C02. The CS4210 also supports four reg-
isters that implement the compare-swap operation needed
for isochronous resource management.
Table 3-1. BAR0+Offset E8h: Note ID and Status Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
RSVD
busNumber
nodeNumber
Table 3-2. GUID Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAR0+Offset 24h-27h
BAR0+Offset 28h-2Bh
GUIDHi Register
GUIDLo Register
node_vendor_ID
chip_ID_Lo
chip_ID_Hi
Revision 1.0
15
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